Emulated-Architecture Memory With Virtual Bank Mapping for Deeper Queues
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Solution Overview
Problem
Conventional memory systems with stacked-die architectures face challenges in achieving high bandwidth utilization due to the need to manage complex timing constraints and resource contention, leading to shallow command-scheduling queues and reduced data bus efficiency.
Innovation Solution
Implementing emulated-architecture memory components that programmably configure fewer logical/virtual memory banks and dies, allowing deeper command-scheduling queues by emulating reduced complexity architectures, and using rank-to-rank deskew circuitry to levelize transactional timing and parallel data paths to eliminate bus turnover delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked-die architecture is used to increase memory capacity, then storage capacity is improved, but device complexity and timing constraint management increase
Solution Approach 1:
The patent segments the physical stacked-die memory architecture into virtual memory banks through emulated-architecture mode. Multiple physical dies are logically organized into fewer virtual banks, reducing the complexity of timing constraint management while maintaining the high capacity provided by stacked dies. The control circuitry implements virtual bank mapping that abstracts the physical complexity from the control logic.
Solution Approach 2:
The patent introduces an intermediary emulated-architecture control layer between the host controller and physical memory dies. This intermediary layer manages the translation between physical memory addresses and virtual bank assignments, handling the timing constraint management complexity centrally rather than distributing it across multiple control circuits.
2Quantity of substance
If physical stacked-die architecture is used, then memory capacity is improved, but command-scheduling queue depth is limited due to resource contention
Solution Approach 1:
The patent segments the command scheduling into virtual bank queues rather than managing all physical dies simultaneously. By emulating fewer virtual banks from multiple physical dies, the control circuitry can maintain deeper scheduling queues for each virtual bank while the physical resource contention is managed through virtualization, effectively increasing overall productivity.
3Productivity
If emulated-architecture mode is implemented, then data bus utilization efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal emulated-architecture control circuitry that can operate in multiple modes: emulated-architecture mode for high data bus utilization and standard physical architecture mode for simplicity. The same control circuitry handles both modes through configurable virtual bank mapping, eliminating the need for separate control logic for different architectural interpretations.
Data Source
AI summary
Stacked-die memory components are programmably configurable to emulate memory architectures having fewer logical/virtual memory banks, bank groups and/or integrated circuit dies than the resident physical quantities of those resources, substantially reducing command scheduling complexity in counterpart host component and thereby enabling deeper scheduling queue implementation and correspondingly higher bus utilization efficiency.