Emulation Condition Code Generation Without Branch Instructions

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Solution Overview

Problem

Conventional methods for emulating computer system architectures require the use of branching instructions to handle condition code settings, which are inefficient and consume resources, especially when emulating architectures like z/Architecture where condition code generation and functionality differ significantly from the source machine.

Innovation Solution

Generating sequences of target machine instructions that directly calculate condition codes such as carry, sign, and overflow codes without using branch instructions, employing short instruction sequences and standard arithmetic or Boolean operations to manipulate bits and flags, thereby avoiding the need for branching instructions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If branch instructions are used to handle condition code settings in emulation, then the emulation can be implemented, but processing efficiency deteriorates and resources are consumed

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidinstruction sequence complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates branch instructions from the emulation process by using alternative instruction sequences that directly set condition codes through arithmetic and logical operations. This removes the harmful element (branch instructions) while preserving the functional outcome of condition code generation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical branching mechanism with a direct calculation approach using arithmetic and logical instructions. Instead of using control flow branching to achieve condition code settings, the system uses mathematical operations to directly compute and set the condition codes, thereby eliminating the need for branch instructions.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Loss of time

If branch instructions are used for condition code generation, then emulation functionality is achieved, but execution time increases

Engineering Contradiction:
Improveexecution timeVSAvoidemulation speed
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent ensures continuous execution of instruction sequences without interruptions from branch instructions. By using direct arithmetic and logical operations to set condition codes, the emulation process maintains continuous forward progression through the instruction stream, eliminating the time loss associated with branch prediction failures and control flow changes.

Inventive Principle:
Principle #20Continuity of useful action

3Adaptability or versatility

If conventional branch-based emulation is used, then condition codes can be set, but target architecture resources are consumed

Engineering Contradiction:
Improveemulation capabilityVSAvoidresource consumption
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent enables the emulation system to set condition codes using the target architecture's own arithmetic and logical instructions rather than relying on branch instructions. This self-service approach uses the target machine's native operations to achieve condition code generation, thereby preserving target architecture resources for other critical functions.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8713289B2Efficiently emulating computer architecture condition code settings without executing branch instructions
Publication Date: 2014.04.29 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US8713289B2 patent drawing
  • US8713289B2 patent drawing
  • US8713289B2 patent drawing

AI summary

Emulation of source machine instructions is provided in which target machine CPU condition codes are employed to produce emulated condition code settings without the use, encoding or generation of branching instructions.