Automated Self-Check for Closed Loop Emulation Replay
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Solution Overview
Problem
Current debug solutions for semiconductor products with asynchronous interfaces are inefficient in isolating the root cause of divergences between test runs, leading to resource wastage and potential shipment of products with bugs due to the lack of a systematic method to filter out noise from oscillating design structures and debug logic.
Innovation Solution
A configuration that filters out non-essential divergences by using spatial and temporal optimizations to focus on user-critical signals and cycles, generating a condensed summary of meaningful divergences that directly impact test success criteria, and storing these in an activity database for comparison across test runs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If comprehensive spatial and temporal checks are performed on the entire design, then all divergences are detected, but resource wastage increases significantly
Solution Approach 1:
The design is segmented into multiple partitions, and the test output is divided into corresponding segments. Each segment is checked independently rather than performing a comprehensive check on the entire design, reducing resource consumption while maintaining detection effectiveness for critical divergences.
Solution Approach 2:
Different checking strategies are applied to different segments of the design based on their importance. User-critical signals and cycles receive focused attention, while less critical areas use reduced checking, optimizing resource allocation across the design spectrum.
2Measurement precision
If comprehensive checks are performed on all design signals, then all divergences are identified, but debug time increases significantly
Solution Approach 1:
User-critical signals and cycles are extracted from the entire design output. The system focuses checking efforts on these extracted critical elements, eliminating the need to analyze all design signals and significantly reducing debug time while maintaining identification of critical divergences.
Solution Approach 2:
Instead of performing exhaustive checks on all design elements, the system performs partial checking focused on user-critical signals and cycles. This partial action approach suffices for debugging purposes since these critical elements are the primary source of test failures.
3Quantity of substance
If all test output signals are analyzed, then complete coverage is achieved, but the ability to isolate root cause divergences decreases
Solution Approach 1:
User-critical signals and cycles are extracted from the complete test output. By focusing on these extracted critical elements, the system reduces the volume of data to be analyzed and simultaneously improves root cause isolation capability, as the extracted signals are specifically those most likely to reveal the source of test failures.
4Extent of automation
If deterministic checking methods are applied to non-deterministic design behavior, then systematic debugging is achieved, but the complexity of handling run-to-run variations increases
Solution Approach 1:
User-critical signals and cycles are identified and extracted before the actual checking process. This preliminary action creates a focused subset of data that reduces run-to-run variations in the checking process, enabling systematic debugging while reducing the complexity of handling non-deterministic behavior.
Data Source
AI summary
A configuration for testing a design of an electronic circuit during a set of clock cycles. The test output of the emulation of a design is filtered based on a received testcase. To filter the test output, for each clock cycle in the testcase, a list of objects associated with a previous clock cycle in test case is identified. One or more objects associated with the one or more commands to be executed during the clock cycle is also identified. An updated list is generated by augmenting the list of objects associated with the previous clock cycle with the one or more objects associated with the one or more commands to be executed during the clock cycle. Output values for objects included in the updated list of objects is selected. The filtered test output is then stored in an activity database.