Encapsulated Vertical Interconnects for Low-Loss 5G Package Substrates
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Solution Overview
Problem
Current semiconductor device packaging technologies face challenges in achieving high-speed interconnections with improved signal integrity, particularly in the 5G frequency range, due to channel impedance discontinuities and electrical insertion loss.
Innovation Solution
The implementation of encapsulated vertical interconnects on the land side of semiconductor packages, using various encapsulation materials and forming techniques such as electroplating and solder printing, to create interconnects with specific form factors that reduce insertion loss and increase interconnect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnect structures are used, then manufacturing is simpler, but signal integrity deteriorates with high insertion loss
Solution Approach 1:
The patent applies parameter changes by modifying the physical dimensions and geometry of interconnect structures. Specifically, it uses microvia diameter ratios (D1/D2 between 0.5-1.5), controlled via diameters (5-50 micrometers), and specific height-to-diameter ratios to optimize signal transmission. These parameter adjustments reduce impedance discontinuities and minimize insertion loss, achieving -4.9 dB at 56 GHz compared to conventional structures.
Solution Approach 2:
The patent employs composite materials by combining multiple encapsulation materials with different dielectric constants (ranging from 2.0 to 4.0) in a layered encapsulation structure. This composite approach allows optimization of signal integrity through material selection, where each layer's material properties are chosen to minimize signal loss and impedance mismatches at interfaces.
2Productivity
If interconnect density is increased, then bandwidth is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the interconnect structure into multiple discrete components: land-side microvias, via fills, and encapsulation layers. Each segment can be manufactured and controlled independently, allowing for modular assembly. The microvias are formed at specific locations with controlled diameters, and the via fills are deposited in discrete steps, enabling precise positioning and reduced manufacturing complexity despite high density.
Solution Approach 2:
The patent uses preliminary action by pre-forming the microvia holes through the encapsulation material before depositing the conductive via fills. This sequence allows precise control of via location and dimensions prior to metallization, ensuring accurate positioning. The encapsulation structure is also prepared in advance with defined geometry, enabling subsequent interconnect formation with high precision.
3Reliability
If encapsulation structure is added, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the encapsulation structure to serve multiple functions simultaneously: it provides mechanical support for the interconnects, electrical insulation between conductive elements, signal transmission medium with controlled dielectric properties, and structural framework for the entire land-side interconnect assembly. This multi-functionality reduces the need for separate components, simplifying the overall device architecture despite the sophisticated performance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved signal integrity and reduced insertion loss, with encapsulated vertical interconnects achieving an insertion loss of -4.9 dB at 56 GHz, compared to -8.5 dB, while maintaining a high interconnect density suitable for 5G applications.
Implementation Method 1
an encapsulation material that contacts the land side and the trace, wherein the encapsulation material includes an encapsulation height
Implementation Method 2
forming techniques such as electroplating and solder printing
Data Source
AI summary
A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.