eNVM Integration with RMG HKMG Modules
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Solution Overview
Problem
Conventional eNVM integration flows are incompatible with replacement metal gate (RMG) high-k/metal gate (HKMG) integration schemes due to step height differences between non-volatile and high-voltage/logic gate stacks, requiring additional CMP steps to achieve coplanar surfaces.
Innovation Solution
The method involves forming substrate portions with different upper surface heights, integrating non-volatile gate stacks with an oxide-nitride-oxide (ONO) stack between two polysilicon layers, and forming high-voltage and logic gate stacks as RMG and HKMG stacks respectively, ensuring their upper surfaces are substantially coplanar, thus eliminating the step height difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional eNVM integration flow is used with ONO stack between two polysilicon layers, then non-volatile memory functionality is achieved, but step height difference is created between non-volatile gate stack and high-voltage/logic gate stacks
Solution Approach 1:
The patent applies local quality by creating different substrate portion heights - a first substrate portion at a first height and a second substrate portion at a second height. The non-volatile gate stack is formed over the first substrate portion while high-voltage and logic gate stacks are formed over the second substrate portion. This local height differentiation compensates for the step height difference caused by the ONO stack, enabling all gate stacks to have substantially coplanar upper surfaces.
2Manufacturing precision
If two CMP steps are performed in RMG HKMG integration scheme, then coplanar surfaces are achieved, but process complexity increases and is incompatible with conventional eNVM integration flow
Solution Approach 1:
The patent applies preliminary action by pre-forming substrate portions at different heights before forming the gate stacks. The first substrate portion is prepared at a first height and the second substrate portion is prepared at a second height in advance. This preliminary height differentiation eliminates the need for subsequent CMP steps to achieve coplanarity, as the gate stacks naturally form with substantially coplanar upper surfaces when formed over the pre-differentiated substrate portions.
3Reliability
If eNVM integration flow is used, then non-volatile gate stack is formed with ONO stack, but compatibility with RMG HKMG scheme is lost due to step height difference
Solution Approach 1:
The patent enables compatibility between eNVM integration flow and RMG HKMG scheme by applying local quality through differentiated substrate portions. The first substrate portion is formed at a first height to accommodate the non-volatile gate stack with ONO stack, while the second substrate portion is formed at a second height for high-voltage and logic gate stacks. This local height differentiation allows the conventional eNVM integration flow to produce coplanar gate stacks, making it compatible with RMG HKMG integration schemes that require coplanar surfaces.
Data Source
AI summary
A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.