Epitaxial Block Layer for FinFET Uniform Growth

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Solution Overview

Problem

FinFET devices face challenges in achieving uniform epitaxial growth and ideal facet formation due to non-ideal epitaxy of source and drain, leading to asymmetric growth and potential leakage paths, which complicates contact placement and current crowding issues.

Innovation Solution

A method involving the formation of a dummy gate, spacer layer, and epitaxial block layer over FinFETs, with recesses created in the substrate before removing the epitaxial block layer to enable uniform epitaxial growth by forming epi material within these recesses, ensuring proper stress and facet formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional lithography and etch techniques are used to pattern isolation trench, then the process is simple and familiar, but the critical dimensions required cannot be achieved

Engineering Contradiction:
Improvecritical dimensionVSAvoidpatterning process
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The isolation structure is segmented into multiple components: shallow trench isolation (STI) oxide layers at different depths, dummy gates, and epi blocks. This segmentation allows each component to be formed with appropriate process techniques, achieving the required critical dimensions through self-aligned processes rather than attempting to pattern the entire isolation structure in a single step.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional planar patterning to three-dimensional vertical structuring. By forming STI oxide in recesses at different depths and creating dummy gates that extend vertically, the isolation structure achieves the required precision through vertical dimension control rather than relying solely on lateral lithographic resolution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If epi growth is performed without proper isolation structure, then the process is simpler, but asymmetric growth and non-ideal facets occur

Engineering Contradiction:
Improveepitaxial growth uniformityVSAvoidisolation structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The shallow trench isolation oxide and dummy gate structures are formed preliminarily before the epitaxial growth step. These pre-formed structures serve as templates and barriers that guide the subsequent epi growth, ensuring uniform and symmetric facet formation. The preliminary structures define the geometry into which the epi material will grow, preventing asymmetric growth patterns.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy gate and STI oxide structures act as intermediary elements between the substrate and the epitaxial growth process. These intermediaries control the growth environment by providing physical barriers and defining the growth geometry, thereby mediating the interaction between the epi material and the underlying structure to achieve uniform growth and ideal facets.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If dummy gate is used to isolate epi junction, then isolation is achieved, but leakage paths still exist through the dummy gate

Engineering Contradiction:
Improveisolation effectivenessVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The dummy gate structure, which initially appears to be a potential leakage path, is converted into a beneficial isolation element. By forming the dummy gate from the same epi material as the source and drain regions and integrating it into the self-aligned process, the structure that could potentially cause leakage instead provides mechanical support and defines the isolation geometry, while the actual electrical isolation is achieved through the STI oxide and junction depth control.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

4Manufacturing precision

If contact area is not positioned high on epi structure, then the epi growth is simpler, but current crowding issues occur

Engineering Contradiction:
Improvecontact positioningVSAvoiddevice performance
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent controls the vertical position of the contact area by adjusting epi growth parameters and the geometry of the underlying STI oxide and dummy gate structures. By changing the depth and dimensions of the isolation recesses and the height of the dummy gate, the contact area is positioned at the optimal height on the epi structure, maximizing current flow efficiency and preventing current crowding while maintaining uniform epi growth.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in uniform epitaxial growth, reducing leakage and current crowding issues, and enhances electrostatic control over carriers, improving the overall performance of FinFET devices.

Implementation Method 1

forming an epi material within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9508850B2Epitaxial block layer for a fin field effect transistor device
Publication Date: 2016.11.29 GLOBALFOUNDRIES US INC
  • US9508850B2 patent drawing
  • US9508850B2 patent drawing
  • US9508850B2 patent drawing

AI summary

Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.