Source/Drain Epitaxial Stack With Dopant Clusters for Contact Resistance

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Solution Overview

Problem

The existing semiconductor technologies face challenges in reducing transistor contact resistance, which limits transistor speed and performance.

Innovation Solution

The proposed solution involves forming clusters of dopants embedded in the source/drain regions of transistors using a doped epitaxial stack, with multiple layers of silicon germanium (SiGe) and varying dopant concentrations to reduce contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If heavily doped source/drain terminals are used, then contact resistance is reduced, but manufacturing complexity increases due to the need for precise dopant cluster formation

Engineering Contradiction:
Improvecontact resistanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source/drain region is segmented into multiple epitaxial layers with different dopant concentrations. The dopant distribution is segmented into a first portion in the first epitaxial layer and a second portion in the second epitaxial layer, allowing precise control of dopant clusters while reducing contact resistance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the source/drain structure are given different dopant concentrations tailored to their specific functions. The first epitaxial layer has a first dopant concentration optimized for its region, while the second epitaxial layer has a second dopant concentration optimized for its region, achieving local optimization of electrical properties

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple layers with varying dopant concentrations are used, then contact resistance is reduced, but device structure becomes more complex

Engineering Contradiction:
Improvecontact resistanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source/drain structure employs a nested multi-layer epitaxial configuration where the first epitaxial layer and second epitaxial layer are stacked vertically. Each layer contains dopant clusters nested within its specific layer, creating a compact vertical structure that reduces lateral space requirements while achieving complex dopant distribution

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The dopant distribution is transitioned from a lateral/planar arrangement to a vertical stacking arrangement. By forming dopant clusters in vertically stacked epitaxial layers, the patent utilizes the vertical dimension to achieve complex dopant concentration profiles without increasing lateral device footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively lowers the contact resistance in the source/drain regions, thereby enhancing transistor performance and speed.

Implementation Method 1

precipitating the second dopant to form a cluster of the second dopant in the second epitaxial layer

Methodology Applied
Scientific EffectPrecipitation: Precipitation

Data Source

PatentUS12336210B2Source/drain structure for semiconductor device
Publication Date: 2025.06.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12336210B2 patent drawing
  • US12336210B2 patent drawing
  • US12336210B2 patent drawing

AI summary

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.