Epitaxial Ferroelectric Memory Elements in 3D NAND
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently integrating epitaxial ferroelectric memory elements into monolithic NAND string structures, requiring innovative methods for forming vertical stacks of single crystalline ferroelectric dielectric layers and semiconductor channels.
Innovation Solution
A method involving the formation of an alternating stack of insulating and sacrificial material layers over a substrate, followed by the creation of vertical semiconductor channels and backside recesses, where single crystalline ferroelectric dielectric layers are formed adjacent to these channels, and electrically conductive layers are deposited in the remaining recesses, enabling the construction of memory stack structures with epitaxial ferroelectric elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to integrate ferroelectric memory elements into monolithic NAND string structures, then device complexity is reduced, but manufacturing precision and uniformity of ferroelectric response deteriorate
Solution Approach 1:
The fabrication process is divided into distinct segments: forming alternating insulating and sacrificial material layers, creating vertical semiconductor channels, forming backside recesses, depositing ferroelectric dielectric layers, and filling with conductive material. This segmentation allows each step to be optimized independently, improving manufacturing precision while managing overall device complexity.
Solution Approach 2:
The alternating stack of insulating and sacrificial material layers is formed in advance before the ferroelectric dielectric layers are deposited. This preliminary action establishes a precise template structure that guides subsequent fabrication steps, ensuring uniformity of ferroelectric response and reducing defects.
2Reliability
If defect density in ferroelectric memory elements is reduced, then reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent employs epitaxial growth to form single crystalline ferroelectric dielectric layers, which fundamentally changes the crystal structure parameters compared to conventional polycrystalline approaches. This parameter change eliminates grain boundaries and reduces defect density, improving reliability. The alternating stack structure provides a controlled template that facilitates this epitaxial growth process.
Solution Approach 2:
The alternating insulating and sacrificial material layers serve as an intermediary structure that enables the formation of single crystalline ferroelectric dielectric layers. This intermediary template provides a controlled environment for epitaxial growth, reducing defects while managing the complexity of creating vertical stacks.
3Productivity
If vertical stacks of single crystalline ferroelectric dielectric layers are formed, then program slope improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar ferroelectric memory elements to vertical three-dimensional stacks. This dimensional change increases storage density and improves program slope by enhancing the electric field distribution. The alternating alternating stack structure provides a self-aligning template that facilitates precise vertical formation while managing manufacturing precision requirements.
Solution Approach 2:
The alternating insulating and sacrificial material layers are formed in advance to create a precise template structure. This preliminary action establishes the vertical geometry and spacing before ferroelectric dielectric layers are deposited, reducing the precision requirements for subsequent steps while achieving the desired vertical stack structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of three-dimensional memory devices with improved ferroelectric memory elements, enhancing device performance by reducing defect density and increasing uniformity of ferroelectric response, thus improving program slope and reducing leakage current.
Implementation Method 1
forming vertical semiconductor channels comprising a respective single crystalline semiconductor material in the openings through the alternating stack
Implementation Method 2
forming vertical stacks of single crystalline ferroelectric dielectric layers, wherein each vertical stack of single crystalline ferroelectric dielectric layers is formed adjacent to a respective one of the vertical semiconductor channels
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel.