Solid-State Devices TRIZ Cases

Laser-ablated via holes receive a liquid precursor that thermally decomposes into a conductive layer, eliminating vacuum pump-down time.

A SONOS memory gate stack uses an ONO structure as a hard mask during second conductive layer formation.

A semiconductor film of PbS quantum dots with coordinated ligands narrows the exciton absorption peak half width to 60 nm or less.

A sacrificial interlayer film enables isotropic removal of insulator residue during cross-point memory pillar etching.

A display substrate uses a patterned conductive layer to disperse electrostatic charges across overlapping metal structures.

A vapor deposition mask with recessed surfaces creates a gap between the tool and substrate to prevent mechanical damage during organic thin film formation.

A shield electrode positioned between pixel and data lines minimizes coupling capacitance in liquid crystal display array substrates.

Direct electrode contact eliminates second insulation layers, resolving manufacturing complexity while maintaining signal stability.

A variable resistance layer uses segmented metal oxides with varying oxygen content to concentrate operation current.

A display device integrates a light blocking pattern to shield transistors from exposure.

A semiconductor light-emitting device uses a reflective protection structure to enhance electrode reliability and light extraction efficiency.

An amine-based buffer layer reduces exciton-polaron quenching at the interface, lowering driving voltage and extending device lifetime.

Vertical capacitor formation reduces horizontal parasitic area, increasing the aperture ratio for IPS LCD array substrates.

Transparent support plate with elongate holes holds optical elements and opaque encapsulation material.

A green MOSFET uses band-to-band tunneling to enhance gate-induced drain leakage current.

An etch stop layer protects buried bit lines from surface damage during subsequent processing, reducing resistance for sub-50 nm DRAM integration.

Vertical conductive member extension reduces surface area while maintaining required capacitance for high integration.

A light emitting device package isolates the phosphor layer from chip heat using adiabatic barriers.

A polymer with electron-donating and accepting units forms a charge-transfer state to enable thermally activated delayed fluorescence.

Graded metal concentration in the electron-transport layer extends driving lifetime by reducing initial decay while maintaining high productivity.

Field-oriented deposition aligns electronic components within conductive cavities, reducing manufacturing complexity and cost for durable displays.

A separated assistance member prevents short-circuiting between the second electrode and data line during laser fusion, reducing pixel defects.

A semiconductor device manages impurity concentration through controlled layer widths to enhance conductivity modulation.

A three-dimensional memory device integrates single crystalline ferroelectric dielectric layers adjacent to vertical semiconductor channels.

Patterned openings in conductive layers block noise light interference while transmitting signal light to improve sensor sensitivity.

Angled gate lines in an array substrate align liquid crystal molecules to improve display viewing angles.

Photo-detecting molecule layer absorbs light to generate charges and secondary electrons that alter variable resistance states in sub-micron pixels.

A bulb-type bottom electrode contact with a larger lower diameter reduces resistance to the switching device in phase-change memory.

A flexible multilayer substrate integrates a light scattering layer to extract trapped light from OLED waveguides.

A reflective coating applied to the carrier and chip lateral surfaces directs electromagnetic radiation away from the semiconductor device.

Combining delayed fluorescent and phosphorescent dopants in a single emitting layer resolves the trade-off between color continuity and emitting efficiency.

Linker-mediated self-assembly positions metallic nanoparticles for stable room temperature operation without complex lithography.

Three-dimensional nano-structures expand the semiconductor interface to boost photon emission density.

Unified mask patterning merges photolithography steps to reduce mask count and production costs while maintaining alignment precision.

A voltage generator produces a temperature-proportional signal to drive the MOS transistor body terminal.

A light guiding group with matched refractive index sits on the phosphor sheet ring region to improve light uniformity.

Flux supply regions in the first ferromagnetic layer constrain domain wall movement, preventing current concentration and heat generation.

A single mask defines threshold adjust and source-drain implants for flash memory NMOS transistors.

A photodetector uses a light shielding resin layer to cover exposed surfaces and prevent stray light from entering detection elements.

A vertical channel semiconductor memory device uses a silicon germanium active pillar to increase charge mobility.

Aluminum oxide and titanium layers prevent oxygen diffusion to improve cycling endurance of resistive memory devices.

Inclined side surfaces on semiconductor layers enable external light emission, reducing internal reflection losses and increasing luminous intensity.

Segmented resin application resolves incomplete coverage bottlenecks, boosting luminous flux by 24%.

Dual light-shielding layers block internal electroluminescence interference, enabling accurate external illuminance detection in organic displays.

A CMOS image sensor fabrication method uses a step height to prevent color filter accumulation during spin coating.

A magneto-resistive memory cell uses separate programming and sensing current paths to optimize heating and reading operations.

A quantum dot device uses a dual hole auxiliary layer structure to enhance charge transport and electron blocking capabilities.

Relocating source contacts to array edges eliminates internal routing overhead, reducing die area while maintaining electrical conductivity.

Embedding methylammonium lead chloride nanopillars in a polymer matrix overcomes roughness issues to boost optoelectronic efficiency.