LCD Fabrication Reducing Masks via Unified Patterning
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Solution Overview
Problem
The existing LCD device fabrication methods require multiple photolithography processes, increasing production costs and reducing yield due to the high number of masks used, which also complicates the application of TFTs with top gate structures.
Innovation Solution
The method reduces the number of masks by simultaneously forming contact holes for the drain electrode and pixel electrode, using a diffraction exposure process to form the active layer and ohmic contact layers in a single masking step, thereby reducing the total number of photolithography processes from seven to five.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography processes are used to fabricate TFT, then the alignment and precision of the structure are improved, but the number of masks increases and production cost increases
Solution Approach 1:
The patent combines multiple photolithography processes into a single process by using a unified mask pattern that defines the active layer, source/drain electrodes, and pixel electrode simultaneously. This merging approach reduces the number of masks from multiple separate masks to a single integrated mask, thereby reducing device complexity while maintaining alignment precision through the unified patterning approach.
Solution Approach 2:
The single mask used in the invention serves multiple functions: it patterns the active layer, defines source and drain electrode positions, and establishes pixel electrode locations. This multi-functional mask replaces what would traditionally require several separate masks, reducing the overall number of masking steps while achieving the same structural precision.
2Manufacturing precision
If multiple photolithography processes are used, then the fabrication precision is improved, but the production time and cost increase
Solution Approach 1:
By merging multiple photolithography steps into a single process using a unified mask, the patent reduces the total number of processing steps. This consolidation maintains fabrication precision through the integrated pattern design while significantly improving production efficiency by eliminating repeated masking, aligning, and development cycles.
Solution Approach 2:
The unified mask is designed in advance to incorporate all necessary pattern information for the TFT structure. This preliminary design approach allows all features to be patterned in a single exposure and development step, avoiding the need for multiple sequential operations and thereby improving production throughput while maintaining precision.
3Stability of the object's composition
If conventional fabrication methods are used for top gate TFT, then the structural integrity is maintained, but the application to flexible substrates is limited
Solution Approach 1:
The patent inverts the conventional TFT structure by placing the gate electrode on top of the active layer rather than beneath it. This top-gate configuration, combined with the simplified single-mask fabrication method, reduces mechanical stress and thermal processing requirements, thereby enabling the use of flexible substrates while maintaining the structural integrity and electrical performance of the TFT.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, increases production yield, and reduces costs by minimizing the number of masks required, while allowing for the application of TFTs with top gate structures to flexible substrates, such as plastic, without compromising alignment or substrate deformation.
Implementation Method 1
using a diffraction exposure process to form the active layer and ohmic contact layers in a single masking step
Data Source
AI summary
A method for fabricating an LCD device includes providing first and second substrates; forming an active layer on the first substrate and forming first and second ohmic contact layers on the active layer; forming a first insulation film on the first substrate; forming a gate electrode on the first substrate; forming a second insulation film on the first substrate; forming a pixel electrode on the first substrate; forming a third insulation film on the first substrate; removing a portion of the first to third insulation film to form first and second contact holes, wherein the first contact hole exposes a portion of the first ohmic contact layer and the second contact hole exposes a portion of the second ohmic contact layer; forming a source electrode electrically connected with the first ohmic contact layer within the first contact hole; forming a drain electrode electrically connected with the second ohmic contact layer and the pixel electrode within the second contact hole; and attaching the first and second substrates.