Vertical Channel Semiconductor Memory Devices Using Silicon Germanium Pillars
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing memory capacity and cell current efficiency, particularly due to the high cost of patterning techniques and limitations in multi-level cell techniques, which hinder the effective enhancement of bits per unit cell.
Innovation Solution
The semiconductor memory device incorporates an active pillar with a first portion made of semiconductor material with higher charge mobility than silicon, such as germanium or silicon-germanium, and a second portion with higher silicon content, along with a gate dielectric layer comprising a tunnel, charge storage, and blocking dielectric layers, to enhance cell current and memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If patterning technique for fine patterns is used to increase memory capacity, then memory capacity increases, but manufacturing cost increases significantly
Solution Approach 1:
The patent changes the material parameter of the active pillar from pure silicon to silicon-germanium alloy with varying germanium content. The first portion has higher germanium content (50-100%) for high charge mobility, while the second portion has lower germanium content (0-50%) for structural stability. This material parameter change enables improved charge transport properties without requiring expensive fine pattern patterning techniques.
Solution Approach 2:
The patent applies local quality by creating distinct regions within the active pillar with different germanium concentrations. The first portion (adjacent to substrate) has high germanium content optimized for charge mobility, while the second portion (upper region) has lower germanium content for mechanical stability and integration. This spatial variation in material composition allows each region to perform its specific function optimally without increasing manufacturing complexity.
2Quantity of substance
If multi-level cell technique is used to increase bits per unit cell, then memory capacity increases, but the technique has fundamental limitations
Solution Approach 1:
The patent fundamentally changes the approach from increasing storage density per cell (MLC) to enhancing charge mobility within the channel. By using silicon-germanium with high germanium content (50-100%) in the first portion of the active pillar, the charge mobility is significantly improved, enabling more reliable and efficient charge transport. This parameter change in material composition offers a viable path forward without the diminishing returns and reliability issues of MLC techniques.
3Reliability
If high germanium content material is used in the first portion of active pillar, then charge mobility increases, but material composition control becomes more difficult
Solution Approach 1:
The patent segments the active pillar into two distinct portions with different germanium content ranges. The first portion (lower region adjacent to substrate) contains silicon-germanium with 50-100% germanium for high charge mobility, while the second portion (upper region) contains silicon-germanium with 0-50% germanium for structural stability. This segmentation allows each portion to be optimized independently within its specific germanium concentration range, making the overall manufacturing process more controllable despite the complexity of high-germanium material processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases charge mobility and cell current, improving memory capacity and reducing cell data read errors, while simplifying fabrication processes by using silicon-germanium layers and oxidizing techniques to create a germanium content gradient.
Implementation Method 1
The first portion may include a semiconductor material of which charge mobility is greater than that of silicon
Implementation Method 2
a gate dielectric layer disposed between the active pillar and the gate electrode
Data Source
AI summary
Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content.


