IPS Array Substrate Vertical Capacitor Layout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In-plane switching (IPS) mode liquid crystal display (LCD) devices face a challenge in maintaining high aperture ratio due to the space occupied by parasitic capacitors, which are formed horizontally and reduce the effective area for pixel electrodes and common electrodes.
Innovation Solution
The array substrate design incorporates a dual-layered passivation film and a gate insulating layer to vertically form capacitors between the common electrode connection line and the drain electrode, and between the drain electrode and the common line, thereby reducing the area occupied by capacitors and enhancing the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If parasitic capacitors are formed horizontally on the same substrate as pixel electrodes and common electrodes, then the capacitors can be easily integrated into the display structure, but the aperture ratio is reduced due to the space occupied by the capacitors
Solution Approach 1:
The patent applies dimensionality change by transitioning capacitor formation from a horizontal plane to a vertical dimension. Multiple capacitors (first, second, third, and fourth capacitors) are formed at different vertical levels using stacked electrode structures. The first capacitor is formed between the first common electrode connection line and the first drain electrode, while the second capacitor is formed between the second common electrode connection line and the second drain electrode, with additional capacitors positioned at different heights. This vertical stacking allows capacitors to be integrated without occupying additional horizontal area, thereby maintaining high aperture ratio while achieving complete capacitor integration.
2Illumination intensity
If the common electrode and pixel electrode are formed to be transparent to ensure luminance, then the display brightness is improved, but the end portions of these electrodes block light, reducing the aperture ratio
Solution Approach 1:
The patent segments the electrode structures into multiple functional parts with distinct roles. The pixel electrode and common electrode are divided into multiple sections (first pixel electrode, second pixel electrode, first common electrode, second common electrode) that are spatially separated and positioned at different locations. This segmentation allows the electrode ends to be strategically positioned away from the light transmission path while maintaining electrical functionality. The segmented structure enables transparent electrode materials to be used for luminance while minimizing light blocking by positioning electrode ends in non-critical areas.
3Area of stationary object
If the aperture ratio is increased to improve light transmittance, then the display efficiency is enhanced, but the space for forming parasitic capacitors is reduced
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension for capacitor formation. Instead of requiring additional horizontal space that would reduce aperture ratio, the capacitors are constructed vertically using multiple stacked electrode layers. The first capacitor is formed between horizontally spaced first common electrode connection line and first drain electrode, while the second capacitor is formed between horizontally spaced second common electrode connection line and second drain electrode, with vertical stacking providing the necessary capacitor volume without increasing horizontal footprint. This approach maintains high aperture ratio while providing sufficient space for all required capacitors.
Data Source
AI summary
An array for an in-plane switching (IPS) mode liquid crystal display device includes a gate line formed on a substrate to extend in a first direction, a common line formed on the substrate to extend in the first direction, a data line formed to extend in a second direction, a thin film transistor formed at an intersection between the gate line and the data line, wherein the thin film transistor includes a gate line, a gate insulating layer, an active layer, a source electrode, and a drain electrode, a passivation film formed on the substrate including the thin film transistor, a pixel electrode formed on the passivation film located on a pixel region defined by the gate line and the data line, the pixel electrode being electrically connected to the drain electrode, a common electrode formed on the passivation film, and a common electrode connection line connected to the common electrode and the common line, wherein the common electrode connection line overlaps with the common line and the drain electrode.