SONOS Memory Gate Stack Formation Sequence
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Solution Overview
Problem
Conventional non-volatile memory (NVM) manufacturing processes face issues with blocking oxide layer thickness control and stability due to the formation sequence of ONO structures, leading to voltage operation instability and quality problems in SONOS memory cells, particularly during the etching process and simultaneous manufacturing of memory and logic areas.
Innovation Solution
The method involves forming a first gate oxide layer and a first gate conductive layer, followed by a photolithography process to create a MOS transistor gate, then forming an ONO structure, and a second gate conductive layer for the NVM transistor gate, where the ONO structure acts as a hard mask, allowing for different electrical resistances and avoiding the conventional sequence that leads to blocking oxide layer loss and thickness control issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the ONO structure is formed before the gate oxide layer, then the charge storage layer can be prepared early, but the blocking oxide layer may be lost during subsequent processes, worsening thickness control and voltage stability
Solution Approach 1:
The patent inverts the conventional formation sequence by creating the gate oxide layer and gate conductive layer before forming the ONO structure. This reversal prevents the blocking oxide layer from being lost during subsequent etching processes, thereby maintaining thickness control and voltage stability while still achieving efficient manufacturing.
Solution Approach 2:
The patent performs preliminary actions by forming the gate oxide layer and gate conductive layer in advance before creating the ONO structure. This preliminary preparation ensures that the gate components are already in place and protected, preventing damage to the blocking oxide layer during later processing steps.
2Productivity
If memory area and logic area are manufactured simultaneously, then productivity is improved, but SiN residue may remain in the ONO structure after etching, worsening product quality
Solution Approach 1:
The patent segments the gate conductive layer formation into distinct steps for memory area and logic area. By separating the etching processes and using the ONO structure as a hard mask during second gate conductive layer formation, the patent prevents SiN residue contamination while maintaining batch manufacturing efficiency.
3Ease of manufacture
If nitride of exposed ONO structure is present during oxide layer growth in logic area, then the manufacturing process is simplified, but oxide layer thickness control is worsened due to inhibition of growth
Solution Approach 1:
The patent introduces the gate conductive layer as an intermediary between the ONO structure and the oxide layer growth environment. This intermediary layer prevents direct contact between the nitride in the ONO structure and the oxide growth process, eliminating growth inhibition while maintaining process simplicity.
Data Source
AI summary
A method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a first gate conductive layer onto the substrate; forming a MOS transistor gate by executing a photolithography process on the first gate conductive layer, and then forming an ONO structure on the substrate; and forming a second gate conductive layer on the ONO substrate, and then forming a NVM transistor gate by executing a photolithography process on the second gate conductive layer.