Flash Memory NMOS Transistor Single Mask Threshold Adjustment
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Solution Overview
Problem
Conventional flash memory cell fabrication processes require additional masking steps to adjust the threshold voltage of NMOS transistors, increasing complexity and cost, as they are formed alongside standard transistors with uniform threshold voltages.
Innovation Solution
A single polysilicon process is used to form NMOS transistors for flash memory cells, where the threshold voltage adjust implantation and heavily doped source/drain implantation are performed using a single mask, allowing individual threshold voltage adjustment without additional masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional masking steps are used to adjust threshold voltage of NMOS transistors in flash memory cells, then threshold voltage adjustment precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the threshold voltage adjustment implant and the source/drain implant into a single masking step. The implant mask simultaneously defines both the channel region (for threshold adjustment) and the source/drain regions, eliminating the need for separate masking operations. This merging of functions reduces process complexity while maintaining the ability to precisely adjust threshold voltage through controlled implant dosage and energy parameters.
Solution Approach 2:
The implant mask serves multiple functions: it defines the channel region for threshold voltage adjustment, defines the source and drain regions, and provides self-alignment for both functions. This multi-functional mask design eliminates the need for additional dedicated threshold adjustment masks, thereby reducing overall device complexity while achieving precise threshold control.
2Reliability
If additional masking steps are used to adjust threshold voltage, then electrical characteristics are improved, but manufacturing cost increases
Solution Approach 1:
By merging the threshold adjustment implant and source/drain implant into a single masking step, the patent reduces the number of photolithography and etching cycles required. This consolidation directly lowers manufacturing costs while maintaining precise electrical characteristic control through optimized implant parameters (dosage, energy, angle) that are applied simultaneously to both the channel and source/drain regions.
3Manufacturing precision
If conventional separate masking processes are used for threshold adjustment and source/drain formation, then manufacturing precision is maintained, but productivity decreases
Solution Approach 1:
The implant mask is designed to pre-establish the self-alignment geometry for both threshold adjustment and source/drain formation in a single step. By performing both implantations through one mask pattern, the patent eliminates sequential masking operations and their associated alignment steps, thereby increasing fabrication throughput while maintaining precise spatial relationships between structures.
Solution Approach 2:
The simultaneous definition of channel and source/drain regions through a single implant mask merges two previously separate fabrication sequences into one operation. This reduces the total number of process steps and improves productivity while maintaining manufacturing precision through the self-aligned nature of the single-step implant process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables tailored threshold voltage settings for flash memory cell NMOS transistors, improving electrical characteristics without increasing cost or process complexity, while maintaining compatibility with existing flash memory cell structures.
Implementation Method 1
a first implantation process to form a first doped region and a second doped region that are self-aligned to the polysilicon gate
Implementation Method 2
the first implantation process uses a high implant dose at a low implant energy
Data Source
AI summary
A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure includes forming a photoresist layer over the semiconductor structure and patterning the photoresist layer using a source/drain mask for the NMOS transistor; forming a first N-type region and a second N-type region by a first implantation process using the patterned photoresist as an implant mask where the first implantation process uses a high implant dose at a low implant energy and the first and second N-type regions form the source and drain regions of the NMOS transistor; forming a channel doped region by a second implantation process using the patterned photoresist as an implant mask where the second implantation process uses a low implant dose at a high implant energy and the channel doped region is formed for adjusting a threshold voltage of the NMOS transistor.