Epitaxial Memory Elements with Self-Aligned Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional non-volatile memory array devices face challenges in increasing density, yield, and reliability due to conflicts between contacts, landing pads, and wiring, as well as cell-to-cell variations in electric and magnetic properties caused by polycrystalline layers with random crystal orientations in Magnetic Tunnel Junctions (MTJs).
Innovation Solution
The memory array device features epitaxially grown memory element layers on a mono-crystalline semiconductor surface, with a seed layer to promote layer-by-layer growth and alignment of crystal lattices between FETs and MTJs, along with self-aligned gate conductors and bit lines to enhance cell uniformity and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FET and MTJ construction methods are used with polycrystalline layers, then manufacturing is easier, but cell-to-cell variations in electric and magnetic properties increase
Solution Approach 1:
The patent changes the fundamental parameter of crystal structure from polycrystalline to single-crystalline by using epitaxial growth. This transformation eliminates random crystal orientations and achieves uniform electric and magnetic properties across all memory cells, directly resolving the contradiction between manufacturing ease and cell uniformity.
Solution Approach 2:
The patent employs composite material structures including epitaxial seed layers, buffer layers, and multiple functional layers (magnetic layers, tunnel barriers, contact layers) grown in sequence. This composite approach maintains crystal lattice alignment while achieving the desired electrical and magnetic properties, resolving the contradiction between manufacturing simplicity and precision.
2Quantity of substance
If density is increased in conventional memory structures, then storage capacity improves, but contacts, landing pads, and wiring conflicts increase
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional vertical stacking with epitaxial layers grown perpendicular to the substrate. This dimensional change allows multiple memory cells to be stacked vertically, increasing density without proportionally increasing wiring complexity, as the epitaxial structure provides inherent alignment and integration pathways.
Solution Approach 2:
The patent implements nested structures where memory elements are integrated within the epitaxial layer stack, with FETs formed in recesses between stacked memory elements. This nesting approach increases density by utilizing vertical space efficiently while sharing common wiring and contact structures across multiple cells.
3Manufacturing precision
If epitaxial growth is used for memory element layers, then crystal lattice alignment and cell uniformity improve, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming epitaxial seed layers and buffer layers before growing the functional memory layers. These preliminary layers establish the crystal lattice structure and orientation, making subsequent epitaxial growth more straightforward and controllable, thereby reducing overall manufacturing complexity while maintaining high precision.
Solution Approach 2:
The patent uses buffer layers as intermediaries between the substrate and the functional memory layers. These buffer layers mediate the epitaxial growth process by providing a suitable crystal template and reducing lattice mismatch, thereby simplifying the manufacturing of high-precision epitaxial structures with uniform properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high-yielding gigabit memory arrays with uniform electric and magnetic properties, improving density, yield, and reliability by maintaining crystal lattice alignment and reducing cell-to-cell variations.
Implementation Method 1
epitaxially grown memory element layers on a mono-crystalline semiconductor surface, with a seed layer to promote layer-by-layer growth and alignment of crystal lattices
Data Source
AI summary
A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element.