Epitaxial Structure Roughened Layer for High-Voltage HEMTs
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Solution Overview
Problem
Conventional doped structures in high electron mobility transistors (HEMTs) suffer from defects and inadequate withstand voltage performance.
Innovation Solution
A method involving sequential low-temperature and high-temperature growth steps to form a roughened layer with intrinsically and extrinsically doped structures, enhancing the epitaxial structure's quality and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a conventional doped structure is used to improve withstand voltage performance, then the withstand voltage performance is improved, but defects are easily caused
Solution Approach 1:
The patent applies parameter changes by implementing a two-stage thermal processing approach: first performing a low-temperature growth step to form an intrinsically doped structure, then performing a high-temperature growth step to form an extrinsically doped structure. This sequential temperature parameter change enables the formation of a roughened layer with improved crystal quality that achieves both high withstand voltage performance and reduced defects, resolving the contradiction between strength improvement and reliability maintenance.
2Strength
If a conventional doped structure is used to enhance withstand voltage performance, then the withstand voltage performance is enhanced, but the epitaxial quality deteriorates
Solution Approach 1:
The patent segments the doping process into two distinct stages: a first low-temperature growth step that forms an intrinsically doped structure, and a second high-temperature growth step that forms an extrinsically doped structure. This segmentation allows each stage to optimize for different requirements - the first stage establishes a high-quality crystal foundation with intrinsic doping, while the second stage enhances withstand voltage performance through extrinsic doping, thereby resolving the contradiction between strength enhancement and manufacturing precision.
Solution Approach 2:
The patent utilizes parameter changes by transitioning from low-temperature processing to high-temperature processing in sequence. The low-temperature first buffer layer formation ensures high epitaxial quality, while the subsequent high-temperature roughened layer formation enhances withstand voltage performance. This controlled parameter evolution resolves the contradiction between improving strength and maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances withstand voltage performance and reduces surface defects, resulting in improved epitaxial quality with reduced leakage current.
Implementation Method 1
the first low-temperature growth step includes forming a first intrinsically doped structure at a first low-temperature
Implementation Method 2
the high-temperature growth step includes forming an extrinsically doped structure at a high-temperature
Data Source
AI summary
A method of manufacturing an epitaxial structure includes: providing a substrate; forming a first buffer layer above the substrate; forming a roughened layer above the first buffer layer, wherein a process of forming the roughened layer includes performing a first low-temperature growth step and a high-temperature growth step; the first low-temperature growth step includes forming a first intrinsically doped structure at a first low-temperature; the high-temperature growth step includes forming an extrinsically doped structure at a high-temperature; the process of forming the roughened layer includes performing the first low-temperature growth step and the high-temperature growth step in sequence at least one time to form the roughened layer; the high-temperature is greater than the first low-temperature; forming a second buffer layer above the roughened layer; and forming a channel layer above the second buffer layer.