Epitaxial Shell Nanowire FET for Device Width Scaling
Solution Overview
Problem
Maintaining effective device width scaling in nanowire field effect transistor (FET) devices is challenging, particularly in gate all around FETs, due to difficulties in controlling the patterning process and achieving reliable yield with small spacing between nanowires.
Innovation Solution
Forming a doped or undoped epitaxial shell around a doped or undoped nanowire core to increase the effective device width, which involves etching nanowire cores and pads in a ladder-like configuration on a semiconductor-on-insulator wafer, suspending them over a buried oxide, and growing epitaxial shells to surround the nanowire cores, thereby increasing the device width while reducing channel-to-channel spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If nanowire cores are patterned with small spacing to maintain device width scaling, then effective device width is maintained, but patterning control becomes difficult and manufacturing reliability decreases
Solution Approach 1:
The device width enhancement is segmented into two independent components: the patterned nanowire core and the epitaxially grown shell. This segmentation allows the core to be patterned at a relaxed pitch while the shell provides the additional width, decoupling the patterning difficulty from the final device width requirement.
Solution Approach 2:
The nanowire cores are patterned first at a larger, more controllable pitch, and then the epitaxial shell is grown subsequently to increase the effective device width. This preliminary patterning action avoids the difficulty of directly patterning nanowires at the final small spacing required for scaled devices.
2Length of stationary object
If stacked layered structures are created to maintain effective device width, then device width scaling is maintained, but process complexity increases
Solution Approach 1:
Instead of stacking nanowires in multiple layers (vertical dimension), the invention grows epitaxial shells radially outward from the nanowire cores (radial dimension). This dimensional change achieves device width enhancement without the process complexity of stacked layered structures.
3Length of stationary object
If large nanowires are patterned with small spacing, then effective device width is maintained, but manufacturing reliability and yield decrease
Solution Approach 1:
The final device width is segmented into the patterned core width plus the epitaxial shell width. This allows patterning of larger-spaced nanowire cores with higher reliability, while the shell contributes the remaining width needed for the scaled device.
Solution Approach 2:
Nanowire cores are preliminarily patterned at larger spacing with better control and higher yield, then the epitaxial shell is grown to achieve the final small effective pitch. This preliminary action at relaxed dimensions improves manufacturing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the active device width and reduces channel-to-channel spacing, simplifying the process flow and improving the reliability of nanowire FET devices by allowing for varying core-to-shell thickness ratios and strain management in the channel region.
Implementation Method 1
Epitaxial shells are formed surrounding each of the nanowire cores
Data Source
AI summary
Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls.