Nanoinformatics TRIZ Cases

A photomask manufacturing method adjusts local reflection coefficients to correct absorber pattern dimensions.

A nanoimprint mold transfers pyramid-shaped patterns to GaN substrates.

A graphene layer contributes quantum capacitance to a varactor dielectric structure.

A back-gated quantum well heterostructure uses a forward-biased halo p-n junction to tune electron wave functions.

Suspension electrodes hold a nanowire above gates to eliminate defects and reduce quantum misalignment in scalable architectures.

Inverted OLED electrode structure with auxiliary and insulation layers resolves crystallization non-uniformity by enhancing hole injection.

Vertical CNT-oxide-metal diodes enable scalable manufacturing of robust THz rectennas by overcoming fabrication difficulties in small geometries.

Air gaps between superlattice structures and fins prevent current leakage while maintaining high drive current.

Anisotropic etching along crystallographic planes defines nanowires from fins with sidewall protrusions, improving shape control.

Segmenting the organic insulating layer with a separation groove prevents water entry, allowing a slim bezel without sacrificing device reliability.

A two-step imprint process uses a flexible polymer stamp to transfer patterns from a template to a substrate surface.

Aromatic divinyl ether formulations eliminate residual layer damage by enabling complete curing, which preserves feature integrity and mask quality.

A polymerizable composition with low viscosity and vapor pressure enables rapid filling of fine relief patterns in imprint lithography.

Growing an epitaxial silicon film compensates for material loss during pillar etching, preventing void defects in source-drain recesses.

Extending the source beneath the gate increases on-state current and reduces variability by providing a larger tunnelling area.

Facet source-drain features and bended inner spacers create an air gap that reduces parasitic capacitance between epitaxial regions and metal gates.

Strained silicon germanium buffer layer induces tensile strain in suspended nanosheets to maintain lateral straightness.

A control system derives derivative acceleration from position measurements to generate compensatory force for vibration dampening.

Epitaxially growing doped semiconductor material on exposed nanowire cross sections to form source and drain regions in omega shaped field effect transistors.

A polymer composition with specific structural units and C70+ fullerenes enhances photoelectric conversion efficiency.

Continuous roller rotation transfers patterns to large substrates, eliminating repetitive step-and-repeat cycles and boosting production efficiency.

A semiconductor device uses a carbon concentration gradient in the work function adjustment film to tune the effective work function.

Computer aided mask design generates prepattern shapes with sub-resolution assist features to guide self-assembly materials.

Continuous semiconductor layer extends between contact regions and dielectric spacers to reduce electrical resistance.

Selective doping diffusion creates a doped region that guides etching to trim nanowire cross-sections while maintaining uniform geometry.

Modulating the superstrate shape directs gas flow to prevent non-fill defects and ensure uniform planarization quality.

Self-aligned barrier gates interdigitated with spin qubit gates reduce manufacturing complexity while improving coherence time through precise alignment.

Growing an epitaxial shell around a patterned nanowire core increases effective device width while maintaining tight channel-to-channel spacing.

A solvent-dissolvable resist layer embeds nanowires to create a planar surface, eliminating shadowing effects during metal electrode deposition.

Discrete data islands incorporate a flux channeling layer with lower anisotropy to reduce writing fields and improve bit-addressability.

Single hydrolysable silane compounds reduce hydrolysis reactions to improve storage stability and prevent thick adhesion layers at substrate ends.

Optical fiber directional couplers combine input photons to enable Bell state measurement via interference patterns.

A method deposits sacrificial and semiconductor layers to form vertically stacked nanowire field effect transistors on a substrate.

Silicon carbide fin templates guide annealing to form graphene nanoribbons, eliminating edge roughness from direct etching.

A graphene semiconductor device uses a sacrificial layer to separate and transfer the semiconductor film onto a base substrate.

A TaNH film absorber layer reduces charge-up during electron beam patterning by modifying electrical properties through hydrogen incorporation.

A recessed insulating fine particle layer accelerates electrons through a second electrode at moderate voltages.

Tri-gate electrostatic doping graphene nanoribbons overcome silicon quantum tunneling limits to deliver high on-off current ratios.

A single-electron transistor uses a metal nanoparticle in a nanogap to perform multiple logic functions via gate voltage adjustments.

A multi-layered epitaxial source/drain region with graded germanium concentrations enhances charge mobility in vertical field effect transistors.

Shallow trench discrete track media structures define magnetic data tracks using reactive plasma treatment to diminish magnetic moment in trench floor regions.

Electron beam-induced deposition creates Josephson junctions from uniform materials in a single step.

Multi-layer sacrificial structures pattern transistor gates across non-volatile memory and logic areas, resolving thick anti-reflective coating non-planarity.

Segmenting the floating gate into nanodots isolates tunnel oxide defects, maintaining reliable charge retention during device scaling.

Gate voltage shifts a local mini-band structure to align or misalign with the conduction band, reducing leakage current and steepening the subthreshold slope.

Vertical carbon nano-tube growth on catalyst layers removes rough surface topography issues caused by direct etching.

Vacuum-based nanocluster deposition creates uniform silicon structures to reduce leakage currents and improve data retention in nano-floating gate memories.

Selective high-k film and metal gate electrode deposition on nanowires reduces leakage current and maintains short channel control beyond the 14 nm node.

A semiconductor structure uses laterally disposed crystalline layers to optimize transistor mobility performance.