Nanosheet Transistor Facet S/D Features Reduce Parasitic Capacitance
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Solution Overview
Problem
The fabrication of nanosheet transistors faces challenges due to high parasitic capacitance between the epitaxial S/D features and the metal gate, caused by high-k materials and limited inner spacer thickness, which can also damage the inner spacers during the fabrication process.
Innovation Solution
The formation of an air gap between the epitaxial S/D feature and the metal gate, with a bended half-ring-shape inner spacer and facet S/D features, reduces parasitic capacitance and protects the inner spacers from damage during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k material is used in the metal gate, then gate control is improved, but parasitic capacitance between the epitaxial S/D features and the metal gate increases
Solution Approach 1:
An air gap is introduced as an intermediary layer between the epitaxial S/D features and the metal gate. This air gap acts as a mediator that reduces the parasitic capacitance while allowing the high-k material in the metal gate to maintain its gate control functionality. The air gap serves as a dielectric spacer that electrically isolates the S/D features from the gate, thereby reducing unwanted capacitive coupling.
Solution Approach 2:
The harmful capacitive coupling is extracted or removed by creating a physical separation (air gap) between the epitaxial S/D features and the metal gate. This extraction of the direct contact interface eliminates the source of parasitic capacitance while preserving the essential gate control function through the high-k material.
2Length of moving object
If inner spacer thickness is reduced, then device scaling is achieved, but parasitic capacitance increases and inner spacers become vulnerable to damage
Solution Approach 1:
The air gap serves as an intermediary that replaces the need for a thick inner spacer. By introducing this air gap between the epitaxial S/D features and the metal gate, the design achieves electrical isolation and reduced parasitic capacitance without requiring a minimum inner spacer thickness, thus enabling further device scaling.
Solution Approach 2:
The design changes the physical state and parameters of the spacer region by replacing solid inner spacer material with an air gap. This parameter change from solid dielectric to air dielectric reduces the parasitic capacitance and eliminates the mechanical vulnerability of thin inner spacers during fabrication processes.
3Length of moving object
If inner spacer thickness is limited, then device miniaturization is achieved, but manufacturing precision is compromised due to damage risk
Solution Approach 1:
The vulnerable inner spacer structure is extracted or removed in the critical region where it would be damaged. Instead of having a continuous thin inner spacer, the design introduces an air gap that eliminates the need for a minimum-thickness inner spacer, thereby removing the source of manufacturing defects and damage risk.
Solution Approach 2:
The air gap serves as a protective cushion or buffer zone between the epitaxial S/D features and the metal gate. This pre-established air gap prevents direct contact and potential damage during subsequent fabrication steps, thereby protecting the structural integrity of the inner spacer region without requiring increased thickness.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises alternately forming first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers include different materials and are stacked up along a direction substantially perpendicular to a top surface of the substrate; forming a dummy gate structure over the first and second semiconductor layers; forming a source/drain (S/D) trench along a sidewall of the dummy gate structure; forming inner spacers between edge portions of the first semiconductor layers, wherein the inner spacers are bended towards the second semiconductor layers; and epitaxially growing a S/D feature in the S/D trench, wherein the S/D feature contacts the first semiconductor layers and includes facets forming a recession away from the inner spacers.