Memory Device Contact Architecture Reducing Resistance
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Solution Overview
Problem
The miniaturization of electronics using conventional materials like silicon is approaching its scaling limit, and 2D materials offer promising properties but face challenges with high contact resistances due to small contact surfaces in side contact configurations.
Innovation Solution
A memory device architecture that eliminates side contact configurations by using a semiconductor layer with second regions extending between contact regions and dielectric spacers, forming a continuous layer that reduces contact resistances and allows for efficient charge transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If side contact configuration is used to deposit metallic contact regions on 2D material, then the contact regions can be formed against the sides of the 2D material layer, but the contact surface between the 2D material layer and the contact regions becomes small, generating significant contact resistances
Solution Approach 1:
The patent transitions from a planar contact configuration to a three-dimensional structure by forming the semiconductor layer as a continuous sheet that extends vertically along the gate structure. This allows contact regions to access the semiconductor layer from multiple spatial positions (top surface and side walls), effectively increasing the contact surface area without increasing the planar footprint, thereby reducing contact resistance while maintaining manufacturability.
Solution Approach 2:
The semiconductor layer is segmented into multiple functional regions: first regions forming the conduction channel, second regions extending along the gate for electrical coupling, and third regions forming source/drain contacts. This segmentation allows each region to be optimized for its specific function while maintaining continuous material connectivity, resolving the contradiction between easy contact formation and low contact resistance.
2Ease of manufacture
If silicon portions are used as support for deposition of 2D material layer, then the 2D material can be deposited, but the silicon portions form a potential barrier at the interface with the 2D material, causing charge transport to occur in the silicon portions rather than the 2D material
Solution Approach 1:
The patent removes the silicon support portions that create potential barriers and extracts only the essential function of support and definition. The gate structure provides the necessary structural definition without forming a continuous conductive path that would compete with the 2D material for charge transport, allowing the 2D material to serve as the primary conduction channel.
Solution Approach 2:
The patent introduces gate dielectric layers as intermediaries between the gate structure and the 2D material layer. These dielectric layers prevent direct contact between the gate and 2D material, eliminating potential barrier formation while still allowing the gate to exert electrostatic control over the conduction channel, thus resolving the contradiction between deposition ease and charge transport reliability.
3Ease of manufacture
If the semiconductor layer is made after the electrostatic control gate, then the conduction channel can be formed, but the semiconductor layer may be damaged by the production steps related to the electrostatic control gate
Solution Approach 1:
The patent forms the complete semiconductor layer (including first, second, and third regions) as a continuous structure before completing the gate production steps. This preliminary formation protects the semiconductor layer from damage during subsequent gate fabrication processes, as the continuous layer structure is more robust and can better withstand the mechanical and chemical stresses of gate production.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed architecture reduces contact resistances, maintains high electric current flow through the conduction channel, and allows for the use of 2D materials without damaging the semiconductor layer during production, enhancing device performance and compatibility with various semiconductor materials.
Implementation Method 1
a semiconductor layer comprising a plurality of first regions superimposed on one another, the first regions forming an electrical conduction channel of the selection transistor
Data Source
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AI summary
Memory device (100) comprising a memory stack (158) electrically connected in series with a selection transistor, comprising: - a semiconductor layer (120) of which first zones (122) are superimposed and form a channel; - an electrostatic control gate (110) and a gate dielectric layer (112) such that portions of the gate dielectric layer are each disposed between a portion (106, 108) of the gate and one of the first zones; - dielectric spacers (114) disposed against flanks of the gate; - contact regions (116, 118) electrically coupled to the first zones by second zones (124) of the semiconductor layer extending between the contact regions and the spacers, one of the contact regions (118) comprising the memory stack; and in which the second zones form, with the first zones, a continuous layer.