Tunnel Field Effect Transistor Source Extension
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Solution Overview
Problem
The existing tunnel field effect transistor (TFET) designs face challenges in producing high-quality gate oxide on SiGe or Ge sources, leading to defects and performance degradation due to the difficulty in forming thick source regions, which limits on-state current and increases variability.
Innovation Solution
A TFET design where the source extends beneath the gate, allowing charge carrier tunnelling to occur over a range of locations rather than a single point, with a thin epitaxial source layer of SiGe or Ge, reducing reliance on a single small region and enhancing on-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a thick source region of SiGe or Ge is produced to enable reasonable on-state current, then the on-state current improves, but the manufacturing precision deteriorates due to difficulty in producing thick source regions with sharp transitions
Solution Approach 1:
The source region is extended in the vertical dimension beneath the gate, creating a three-dimensional structure that increases the tunnelling volume. This dimensional change allows the source to provide sufficient carriers for good on-state current while maintaining a sharp horizontal transition at the surface, resolving the conflict between thick source requirement and sharp transition manufacturing precision.
Solution Approach 2:
The source region is nested beneath the gate structure, with the channel region positioned between the gate and the source. This nested arrangement allows the source to extend deeply into the substrate while maintaining a clean interface with the channel, enabling both thick source for current and sharp transitions for manufacturing precision.
2Reliability
If gate oxide is formed on the source surface to electrically isolate the gate, then the electrical isolation improves, but the reliability deteriorates due to difficulty in producing high quality oxide on SiGe or Ge
Solution Approach 1:
The gate oxide formation process is extracted from the SiGe/Ge source surface and applied only to the silicon channel region. By separating the oxide formation location from the problematic SiGe/Ge source material, the patent achieves reliable electrical isolation without the manufacturing difficulties of forming high-quality oxide on germanium-based materials.
Solution Approach 2:
The silicon channel region acts as an intermediary layer between the gate oxide and the SiGe/Ge source. This intermediate silicon layer provides a suitable substrate for high-quality oxide formation, while the source remains beneath the gate structure, eliminating the direct need for oxide on SiGe/Ge surfaces.
3Power
If tunnelling is limited to a single point-like region at the gate oxide-channel interface, then the device structure simplifies, but the productivity deteriorates due to limited on-state current
Solution Approach 1:
The tunnelling mechanism is extended from a two-dimensional interface phenomenon to a three-dimensional volume phenomenon by positioning the source beneath the gate. This dimensional extension creates multiple tunnelling paths throughout the source volume, increasing the total on-state current while maintaining a relatively simple planar device structure.
Solution Approach 2:
The single point-like tunnelling region is segmented into multiple distributed tunnelling sites throughout the source volume beneath the gate. This segmentation of the tunnelling function across multiple locations increases the total current capacity while distributing the functional load, effectively increasing productivity without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases on-state current and reduces performance variability by providing a larger tunnelling area and improving the quality of the source-channel interface, mitigating the impact of defects and stress-related issues.
Implementation Method 1
the transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source
Implementation Method 2
tunnel field effect transistor (TFET)... an inversion layer 3 induced in the channel region by the gate potential
Data Source
AI summary
A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.