Nanowire Fabrication via Anisotropic Etching of Sidewall Protrusions
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Solution Overview
Problem
The fabrication of nanowire structures for CMOS transistors is challenging due to difficulties in integrating nanowire fabrication techniques into integrated circuit processes, particularly in controlling the shape and surface geometry of nanowires, which affects circuit structure properties and performance.
Innovation Solution
A method involving the formation of fins with elongate sidewall protrusions, followed by anisotropic etching along a pre-defined crystallographic plane to define nanowires, using etchants like ammonium hydroxide or tetramethyl ammonium hydroxide to create nanowires with surfaces bounded by a (111) crystallographic plane, allowing for improved control over nanowire shape and geometry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional nanowire fabrication techniques are used, then nanowire structures can be formed, but control over nanowire shape and surface geometry is poor
Solution Approach 1:
The method forms fins with pre-defined crystallographic orientations and elongate sidewall protrusions before the nanowire definition step. This preliminary structuring enables precise control over the subsequent nanowire shape and geometry, as the anisotropic etching process follows the pre-established fin geometry to create nanowires with specific crystallographic planes
Solution Approach 2:
The invention utilizes changes in crystallographic orientation parameters by forming fins with specific orientations and using anisotropic etching along pre-defined crystallographic planes. This parameter control allows precise definition of nanowire shape and surface geometry, creating nanowires bounded by specific crystallographic planes such as (111) planes
2Length of moving object
If transistor size is reduced to improve scaling, then circuit density increases, but short-channel effects worsen
Solution Approach 1:
The invention transitions from planar gate control to three-dimensional gate-all-around control by forming nanowire channels with gates wrapping around all surfaces. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short-channel effects even as transistor dimensions are reduced for scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the fabrication of nanowires with precise control over shape and surface geometry, enhancing gate controllability and minimizing short-channel effects in CMOS transistors, thereby improving circuit performance.
Implementation Method 1
anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires
Implementation Method 2
creating nanowires with surfaces bounded by a (111) crystallographic plane
Data Source
AI summary
Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.