Epitaxial Vertical Channel Orientation for 3D NAND On-Current
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Solution Overview
Problem
As the number of word lines increases in three-dimensional memory devices, the length of vertical semiconductor channels in NAND strings grows, leading to a decrease in on-current, necessitating a solution to enhance on-current and enable vertical scaling while maintaining or increasing the number of word lines.
Innovation Solution
The implementation of epitaxial vertical semiconductor channels, which are formed by growing single crystalline semiconductor material in epitaxial alignment with the substrate, within memory openings, to increase charge carrier mobility and enhance on-current, allowing for a greater number of word lines without voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased, then the memory density is improved, but the vertical semiconductor channel length increases leading to decreased on-current
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the semiconductor channel from conventional <100> to <110> orientation. This parameter change increases charge carrier mobility by approximately 2x compared to <100> oriented channels, thereby maintaining high on-current even as channel length increases with additional word lines. The epitaxial growth process enables precise control of this crystallographic orientation parameter.
Solution Approach 2:
The patent employs a composite structure combining epitaxially grown single-crystalline semiconductor material with specific doping profiles. The epitaxial layer provides the optimized <110> crystal orientation while doping regions (n-type and p-type) are strategically placed to enhance carrier concentration and mobility in the channel region, creating a composite material system that overcomes the on-current degradation issue.
2Quantity of substance
If the vertical semiconductor channel length is increased to accommodate more word lines, then the memory capacity is improved, but the charge carrier mobility decreases
Solution Approach 1:
The patent fundamentally changes the crystallographic orientation parameter from <100> to <110> in the vertical semiconductor channel. This parameter change exploits the higher charge carrier mobility inherent to <110> oriented silicon channels, which maintain high mobility even at increased lengths. The epitaxial growth technique enables precise control of this orientation parameter throughout the vertical channel structure.
3Ease of manufacture
If conventional semiconductor channels are used, then the manufacturing process is simpler, but the on-current is insufficient for high-density memory
Solution Approach 1:
The patent performs preliminary action by establishing the correct <110> crystallographic orientation during the epitaxial growth stage, before subsequent processing steps. This preliminary establishment of the optimal crystal orientation ensures that all subsequent manufacturing steps work with a pre-optimized channel structure, achieving high on-current without significantly increasing overall process complexity.
Solution Approach 2:
The patent introduces a specific parameter change - the crystallographic orientation to <110> - during epitaxial growth. This single parameter change provides approximately 2x improvement in charge carrier mobility compared to conventional <100> channels, delivering the required on-current performance for high-density memory while maintaining compatibility with existing CMOS fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of epitaxial vertical semiconductor channels increases the on-current of vertical channels, enabling the stacking of more word lines and improving device density in three-dimensional memory devices without compromising the peripheral circuitry.
Implementation Method 1
filling volumes of the memory openings that are not filled with the memory films with single crystalline semiconductor channel material portions having a doping of a first conductivity type and in epitaxial alignment with the single crystalline substrate semiconductor material
Data Source
AI summary
A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.