Symbol-Domain Interleaving Behind Equalizers for Burst Error Separation

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Solution Overview

Problem

Current forward error correction (FEC) systems in optical data transmission face challenges in effectively separating error bursts into single errors, which affects bit error rate (BER) and hardware resource utilization.

Innovation Solution

The implementation of a receiver, interleaving, and deinterleaving circuit and method that utilizes a Benes network and pseudo random binary sequences (PRBS) to scramble and descramble data, separating burst errors into isolated single errors through irregular link patterns and permutation controllers, optimizing hardware resource use.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If MLSE equalizer is used to combat inter-symbol interference, then signal quality is improved, but error bursts are generated instead of being eliminated

Engineering Contradiction:
Improvesignal qualityVSAvoiderror bursts
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies segmentation by dividing error bursts into smaller units through interleaving. The MLSE equalizer output is interleaved in the symbol domain, which separates consecutive error bursts into isolated single errors or small error groups that are more easily handled by FEC codes. This transforms the harmful concentrated error bursts into manageable segmented errors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary component - the symbol-domain interleaver - between the MLSE equalizer and the FEC decoder. This intermediary transforms the error pattern from burst form to dispersed form, making the errors more suitable for correction by the FEC code. The interleaver acts as a mediator that converts one error type into another more manageable type.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If conventional FEC codes are used without error burst separation, then implementation is simpler, but correction effectiveness is reduced due to error bursts

Engineering Contradiction:
Improveimplementation simplicityVSAvoiderror correction effectiveness
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by performing error burst separation through interleaving before the FEC decoding process. The symbol-domain interleaver is applied to the MLSE equalizer output prior to FEC decoding, preparing the error pattern in advance to be more amenable to correction. This preliminary transformation of error patterns significantly improves FEC effectiveness without adding complex decoding algorithms.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If bit-domain interleaving is used to separate error bursts, then error dispersion is improved, but hardware resource utilization deteriorates

Engineering Contradiction:
Improveerror dispersionVSAvoidhardware resource utilization
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from bit-domain interleaving to symbol-domain interleaving, changing the dimension of operation. Instead of interleaving individual bits, the system interleaves symbols (groups of bits), which achieves effective error dispersion while requiring fewer hardware resources. This dimensional change from bit-level to symbol-level operation reduces the complexity of the interleaving structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the fundamental parameter of interleaving granularity from bit-level to symbol-level. By operating at the symbol domain rather than bit domain, the system achieves the same error separation effect with reduced hardware resources. The symbol-domain approach uses larger units for interleaving, reducing the number of interleaving operations needed.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8874988B2Modification of error statistics behind equalizer to improve inter-working with different FEC codes
Publication Date: 2014.10.28 CISCO TECHNOLOGY INC
  • US8874988B2 patent drawing
  • US8874988B2 patent drawing
  • US8874988B2 patent drawing

AI summary

This invention relates to a receiver circuit which comprises an equalizer (27) and an error decorrelator (25). The error decorrelator being configured for changing (501; 601, 602) the position of symbols. The invention further relates to a corresponding method. This invention finally relates to an interleaving or deinterleaving method which comprises selecting a first number of symbols (204; 302) within a stream of digital data (13; 28) thereby obtaining selected symbols. The method further comprises exchanging (601, 602) the position of at least half of said first number of symbols of said selected symbols with the position of other symbols from said selected symbols. The invention further relates to an interleaving or deinterleaving circuit.