Other Error Detection/Correction/Protection TRIZ Cases
- Memory Controller Parity Interfaces for Reliable Data Transmission
Parity bits generated and checked across interface controllers detect transmission errors with less added controller complexity.
- Selective Speech Frame FEC for Packet Loss Protection
Selective FEC protects critical speech frames against packet loss, preserving voice quality without adding delay or excessive bandwidth.
- Turbo Product Encoder Parallel Row-Column FEC Architecture
Parallel row and column FEC encoding cuts clock cycles and hardware burden in turbo product code generation.
- LDPC Decoder Row Scheduling for Arbitrary Coding Rates
Dynamic row scheduling and stored matrix flags let one LDPC decoder support different coding rates without circuit changes or throughput loss.
- Codeword Detection in Multi-Level Memory Under Signal Drift
Ordered and averaged user-cell read signals estimate drifting reference levels, improving multi-level codeword detection without reference cells.
- Symbol-Domain Interleaving Behind Equalizers for Burst Error Separation
A symbol-domain interleaver behind the equalizer disperses burst errors for stronger FEC decoding with lower BER and simpler hardware.
- Modified Hamming Codes for Incomplete Non-Binary Error Channels
Tailored code words use modified Hamming separation to correct and detect errors in non-binary channels and memories with incomplete transitions.
- Critical Speech Frame FEC Using Channel Feedback
Channel-guided selective FEC protects critical speech frames to preserve voice quality under packet loss without adding end-to-end delay.
- LDPC Channel Encoding with Group Shortening for Matrix Reuse
A group-based LDPC shortening pattern reuses one parity check matrix across codeword lengths and code rates without extra memory.
- Matrix Memory Interleaver for Constant-Rate Turbo Decoding
A matrix memory and FIFO address queue keep symbol output constant, cutting interleaver latency and power in Turbo decoding.
- LDPC Decoding with Offset-Corrected Row LLR Calculation
Minimum-based offset correction makes LDPC row LLR updates closer to Sum-Product decoding, improving precision with fewer arithmetic operations.
- Signature Field Checksum Cheater for Network Latency Frames
A checksum-cheater signature field adds timestamp data after checksum calculation, preserving validity and improving latency frame rates.