LDPC Decoder Row Scheduling for Arbitrary Coding Rates
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Solution Overview
Problem
Existing LDPC code decoders struggle to decode codes with arbitrary coding rates without changing the circuit configuration and face inefficiencies in processing throughput and error detection frequency.
Innovation Solution
A low-density parity-check (LDPC) codes decoder is designed with a decoding control section that manages channel data and generates addresses for parallel column and row processing, utilizing permutation matrices and validity flags to handle different coding rates and improve throughput without degrading quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fully parallel design is adopted to achieve high throughput, then processing throughput is improved, but the decoder cannot decode LDPC codes with different check matrices
Solution Approach 1:
The patent introduces a dynamic control mechanism that adjusts the processing order of rows based on processing wait information. The start instruction postponing means dynamically delays row processing starts to satisfy data availability constraints, enabling the same hardware to adapt to different check matrices while maintaining parallel processing efficiency.
Solution Approach 2:
The patent segments the decoding process into independent row processing units that can be executed in different orders. By dividing the check matrix into multiple rows and allowing flexible processing sequences, the system achieves both high throughput through parallelism and adaptability to different coding rates.
2Adaptability or versatility
If the circuit configuration is changed to decode LDPC codes with different coding rates, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal decoder architecture that can handle multiple coding rates without configuration changes. The key is storing processing wait information for each row in advance, which allows the same hardware to adapt to different check matrices through software-controlled processing sequences rather than hardware reconfiguration.
Solution Approach 2:
The patent introduces processing wait information as an intermediary data structure that mediates between the fixed hardware architecture and variable decoding requirements. This intermediary layer enables flexible adaptation to different coding rates without modifying the underlying circuit configuration.
3Reliability
If error detection is performed frequently during decoding, then reliability is improved, but processing throughput decreases due to delays
Solution Approach 1:
The patent enables continuous error detection during the decoding process by utilizing the dynamic row processing control mechanism. Error detection can be performed at multiple checkpoints without interrupting the overall decoding flow, as the start instruction postponing means allows flexible scheduling that accommodates detection operations.
Data Source
AI summary
A low density parity check codes decoder decodes an LDPC code with an arbitrary coding rate by the same configuration. The low density parity check codes decoder enables decoding of an LDPC code constituted by a base matrix of Mbmax rows and Nbmax columns and a permutation matrix as an element of the base matrix. It stores therein Mbmax×Nbmax validity/invalidity flags, shift amounts of valid permutation matrices, a permutation matrix size in a processing target code, and the number of rows of a base matrix in the processing target code, determined depending on a check matrix for the processing target LDPC code, and generates column addresses and a row address to be given to column processing calculation sections and a row processing calculation section that perform calculation in accordance with a BP algorithm by utilizing the stored information, so that it can process an LDPC code for a smaller base matrix than the aforementioned base matrix as well.