Turbo Product Encoder Parallel Row-Column FEC Architecture
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Solution Overview
Problem
Traditional turbo product code (TPC) encoders in digital communications face inefficiencies in encoding speed and hardware usage due to serial processing of parity bits, which limits their ability to handle large codewords effectively.
Innovation Solution
The proposed solution involves a parallel processing architecture where multiple information bits are processed in a single clock cycle using a row encoder and multiple column encoders operating in parallel, with a multiplexing system to combine and output FEC bits efficiently, reducing the number of clock cycles required for encoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial processing of parity bits is used in traditional TPC encoders, then hardware complexity is reduced, but encoding speed and productivity deteriorate
Solution Approach 1:
The encoder is segmented into multiple parallel processing units: a row encoder for processing rows of information bits and multiple column encoders for processing columns in parallel. This segmentation allows simultaneous computation of multiple parity bits, dramatically increasing encoding speed while maintaining manageable hardware complexity through modular architecture
Solution Approach 2:
The encoder transitions from one-dimensional serial processing to two-dimensional parallel processing by organizing encoders in a grid structure with row and column dimensions. Multiple column encoders operate simultaneously on different columns while the row encoder processes rows, creating a dimensional expansion that boosts productivity without proportionally increasing hardware complexity
2Productivity
If multiple column encoders operate in parallel, then encoding productivity increases, but device complexity increases
Solution Approach 1:
Multiple column encoders are designed with identical, universal architecture that can process different columns using the same hardware template. This multi-functionality allows the system to achieve parallel processing capability while reusing the same circuit design, thereby increasing productivity without proportionally increasing overall hardware complexity
Solution Approach 2:
The system changes the parameter of parallelism by configuring a specific number of column encoders (e.g., 8 column encoders for a (128,120) code) to achieve optimal encoding speed. This parameter adjustment allows tuning of the balance between productivity and hardware complexity based on specific application requirements
3Device complexity
If traditional serial processing is used, then hardware requirements are reduced, but encoding time increases
Solution Approach 1:
The parallel architecture enables continuous useful action by having multiple column encoders and the row encoder operating simultaneously without idle waiting periods. While the row encoder processes one row, multiple column encoders process multiple columns in parallel, eliminating the sequential waiting time inherent in traditional serial processing and significantly reducing total encoding time
Solution Approach 2:
Multiple column encoders perform preliminary action by pre-computing column parity bits for multiple columns simultaneously while the row encoder is still processing. This preliminary parallel computation overlaps with row processing, reducing the total encoding time without requiring additional hardware resources beyond the parallel encoder structure
Data Source
AI summary
A source controller provides a block of n×a information bits as n separate rows each with a information bits. A row encoder has an input coupled to an output of the source controller and includes a plurality of accumulators arranged to process m of the information bits in one clock cycle to generate row forward error correction FEC bits. At least one column encoder has an input coupled to an output of the source controller and is arranged to generate column FEC bits in parallel with the row encoder. A multiplexer is coupled to outputs of the row and column encoders and is adapted to serially output an nth row of information bits followed by the nth row FEC bits for each of the n rows, followed by additional rows of FEC bits generated by the column encoder. The terms n, m, and a are integers greater than one. Where more than one column encoder is used, there are preferably m column encoders in parallel and each operating at one bit per clock cycle.