Matrix Memory Interleaver for Constant-Rate Turbo Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data communication systems face challenges in reliably transmitting large amounts of data at higher rates with lower channel signal-to-noise ratios, as conventional error correction schemes are overwhelmed by burst errors, and current interleavers introduce latency and power consumption issues when used with Turbo coding.
Innovation Solution
The implementation of an interleaver and de-interleaver system that uses a matrix memory structure to permute data, allowing for efficient interleaving and de-interleaving processes, which reduces latency and power consumption by ensuring symbol data is output at a constant rate, thereby supporting Turbo coding without the need for increased clock rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock rate is increased to give the interleaver clock cycles to skip data, then the interleaver can handle Turbo decoding requirements, but the power consumption increases
Solution Approach 1:
The patent implements a dynamic clocking scheme where the interleaver operates at variable clock rates. During normal operation, it runs at a lower clock rate to conserve power. When data skipping is required for Turbo decoding, it dynamically increases the clock rate temporarily. This dynamic adjustment resolves the contradiction by providing high reliability only when needed while minimizing power consumption during steady-state operation.
2Productivity
If the interleaver skips or discards certain data to maintain constant symbol output rate, then the MAP decoder can operate efficiently, but latency is introduced in the data stream
Solution Approach 1:
The patent employs a buffer memory that preliminarily stores incoming symbol data before it reaches the interleaver. This buffer accumulates data in advance, allowing the interleaver to skip problematic data points without causing downstream latency. The preliminary storage action ensures that the MAP decoder receives a steady stream of valid symbols, maintaining decoder efficiency while minimizing the impact of data skipping on overall system latency.
3Reliability
If conventional error correction schemes are used, then the system can handle uniform errors, but burst errors overwhelm the correction capability
Solution Approach 1:
The patent applies segmentation by dividing the continuous data stream into discrete symbol blocks that are processed individually through the interleaver. Each symbol is treated as a separate unit that can be skipped or passed independently. This segmentation allows the system to isolate burst errors to specific symbols rather than allowing them to corrupt continuous sequences, thereby maintaining error correction capability even in the presence of burst errors.
Data Source
AI summary
Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)−K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)−K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.