Erase Control Circuit Step Voltage Adjustment for NAND Flash Overshoot
Solution Overview
Problem
Current NAND type flash memory devices face challenges in accurately controlling the erase voltage, particularly during 1 plane operation, leading to overshoot and reduced memory cell performance due to variations in rise time, maximum voltage, and pulse width.
Innovation Solution
An erase control circuit and method that utilize a slope adjustment circuit to generate an erase voltage with a step shape by controlling the step voltage, target voltage, and step width, ensuring consistent rise time and preventing overshoot.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high voltage pulse is applied to erase data in memory cells, then the erasure function is achieved, but the rise time variation causes overshoot and reduces memory cell performance
Solution Approach 1:
The erase voltage pulse is segmented into multiple steps with different voltage levels and durations. Instead of applying a single high voltage pulse, the circuit applies a sequence of voltage steps (e.g., first step at lower voltage for longer duration, second step at higher voltage for shorter duration) to achieve the erasure effect while controlling the rise time and preventing overshoot that would occur with a single abrupt voltage application.
Solution Approach 2:
The erase control circuit dynamically adjusts the voltage level and pulse width based on the operation mode (1 plane or 2 plane). The circuit includes voltage selection logic that switches between different voltage configurations depending on the load condition, allowing optimal erase performance for each mode while preventing overshoot and maintaining memory cell reliability.
2Reliability
If the analog circuit is designed for the worst load condition during 2 plane operation, then the erase function is guaranteed for 2 plane operation, but the rise time becomes too fast during 1 plane operation causing overshoot
Solution Approach 1:
The erase control circuit dynamically adapts its voltage output based on the operational mode. When 1 plane operation is detected, the circuit selects voltage parameters optimized for that mode (slower rise time, different step configuration). When 2 plane operation is detected, it switches to parameters optimized for the heavier load. This dynamic adaptation ensures reliable erasure in both modes while preventing overshoot in 1 plane operation.
Solution Approach 2:
The circuit changes key voltage parameters (voltage level, pulse width, step configuration) based on the operation mode. For 1 plane operation, it uses parameters that produce a controlled, slower rise time. For 2 plane operation, it uses parameters optimized for the higher load demand. This parameter switching resolves the contradiction between ensuring erase function and preventing overshoot.
3Productivity
If a single high voltage pulse is applied for erasing, then the process is simple and fast, but the current is very sensitive to parameters such as rise time, maximum voltage, and pulse width
Solution Approach 1:
The single high voltage pulse is segmented into multiple controlled steps with different voltage levels and durations. This segmentation allows precise control over the voltage application profile, reducing sensitivity to parameter variations while maintaining erasure effectiveness. The multi-step approach provides better control without requiring complex external circuitry.
Solution Approach 2:
The erase control circuit integrates the voltage control logic directly into the memory device, allowing it to self-regulate the erase voltage parameters based on its own operational state. The circuit automatically selects appropriate voltage steps and pulse widths based on the detected operation mode, eliminating the need for external control complexity while maintaining precise parameter control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more accurate control of the erase voltage, preventing overshoot and maintaining memory cell performance by adjusting the step voltage, target voltage, and step width, thereby improving data erasure precision.
Implementation Method 1
erasing is to apply a high voltage of 20V, for example, to the semiconductor substrate and apply 0V to the word line. Thereby, electrons are extracted from the floating gate which is a charge storage layer
Implementation Method 2
An erase control circuit and method that utilize a slope adjustment circuit to generate an erase voltage with a step shape by controlling the step voltage, target voltage, and step width
Data Source
AI summary
The erase voltage controlled with higher accuracy than the related art when erasing data in a non-volatile semiconductor memory device is provided. An control circuit for controlling an erase voltage includes: a slope adjustment circuit that controls a slope having a step shape by controlling a step voltage, a target voltage, and a step width of the erase voltage. The slope adjustment circuit repeatedly increases the erase voltage by the step voltage for each predetermined clock pulse control signal to the target voltage based on the step voltage and the target voltage, and outputs the clock pulse control signal to the erase voltage generation circuit by repeatedly clocking each time interval corresponding to the step width based on the step width.