Error Recovery Circuit Bypass for Metastable Signal Handling
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Solution Overview
Problem
Data processing apparatuses face delays due to metastability in error signals generated by error detection units, which hinder operating speed improvements when errors occur, especially at high clock speeds or low voltages.
Innovation Solution
Incorporating error value generation and stabilisation circuitry with count and bypass circuitry to determine if error value stabilisation is necessary, allowing direct bypass of stabilisation procedures if sufficient re-sampling occurs, thereby reducing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stabilisation circuitry re-samples the error signal multiple times to remove metastability, then reliability of error signal is improved, but processing time increases causing delay
Solution Approach 1:
The error value is re-sampled in advance as it propagates through the pipeline stages before reaching the stabilisation circuitry. Count circuitry tracks these preliminary re-sampling operations, and when a sufficient number of re-samples have occurred (counter reaches zero), the stabilisation circuitry can be bypassed, thus performing the stabilisation action beforehand rather than waiting until the error value arrives at the stabilisation stage.
Solution Approach 2:
The system dynamically adjusts the error handling path based on the counter value. When the counter indicates sufficient re-sampling has occurred, the bypass circuitry activates to skip the stabilisation procedure. When the counter indicates insufficient re-sampling, the normal stabilisation path is taken. This dynamic adaptation allows the system to optimize between speed and reliability on a per-error-value basis.
2Productivity
If the data processing apparatus operates at high clock speed or low voltage, then productivity is improved, but error occurrence rate increases
Solution Approach 1:
The error detection units continuously monitor signals and provide feedback when errors are detected. The system uses this feedback to trigger appropriate error handling procedures, including the dynamic bypass decision based on re-sampling counts. This feedback mechanism allows the system to maintain high operating speeds while having reliable error detection and recovery capabilities when needed.
Solution Approach 2:
The system changes the operational parameters dynamically - when operating at high clock speeds or low voltages where errors are more likely, the error detection and re-sampling mechanisms become more active. The counter-based bypass system adjusts the level of stabilisation applied based on the operating conditions and the specific error value being processed, allowing optimized performance across different operating regimes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster error handling and reduced delays in data processing operations by determining if error value stabilisation is required, thus enhancing the operating speed of data processing apparatuses.
Implementation Method 1
some metastability of the error signal generated by the error detection unit can occur
Implementation Method 2
perform a stabilisation procedure on the error value, the stabilisation procedure comprising re-sampling the error value to remove metastability from the error value
Data Source
AI summary
A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.