Low-Leakage ESD Protection Circuit With Bias-Controlled Discharge
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Solution Overview
Problem
Existing ESD protection devices with large transistors (BigFETs) exhibit high leakage current in standby mode, adversely affecting performance and lifetime of semiconductor systems.
Innovation Solution
Incorporating a biasing circuit that suppresses leakage current by biasing the discharge circuit with specific voltage conditions (VGS<0 and VSB>0 or VGS>0 and VSB<0) during standby mode, using diodes and transistors with different types to reduce current flow through the discharge path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large transistors (BigFETs) are used in ESD protection devices, then ESD protection capability is improved, but leakage current in standby mode increases
Solution Approach 1:
The ESD protection device is divided into multiple transistor units (first transistor unit and second transistor unit) with different configurations. Each unit handles specific current paths, allowing the system to maintain ESD protection capability while reducing overall leakage current by optimizing each segment's characteristics.
Solution Approach 2:
Different regions of the device are assigned different functions: the first transistor unit is optimized for ESD protection with higher leakage tolerance, while the second transistor unit is optimized for low leakage in standby mode. This local differentiation allows simultaneous achievement of both ESD protection and low standby current.
2Reliability
If large transistors are used to protect against ESD events, then protection effectiveness is improved, but device lifetime is reduced due to high standby current
Solution Approach 1:
The protection device is segmented into multiple transistor units that share the protection function. This segmentation allows the system to maintain adequate ESD protection while distributing the standby current burden, thereby reducing overall power consumption and extending device operational lifetime.
Solution Approach 2:
The invention changes key parameters of the transistor units, including threshold voltages and channel widths, to optimize the balance between protection effectiveness and standby current. By carefully selecting these parameters, the device achieves sufficient ESD protection with minimized leakage current, extending its operational lifetime.
3Reliability
If discharge circuit is designed for high ESD current handling, then ESD protection is improved, but standby mode performance deteriorates due to current leakage
Solution Approach 1:
The discharge circuit is segmented into multiple transistor units with specialized roles. The first unit is designed for high-current ESD events, while the second unit is optimized for low-leakage standby operation. This segmentation allows the circuit to excel in both ESD protection and standby performance without compromise.
Solution Approach 2:
Different portions of the discharge circuit are given different quality characteristics: one portion emphasizes high current handling for ESD events, while another portion emphasizes low leakage for standby mode. This local quality differentiation resolves the contradiction between protection capability and standby performance.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device comprises a detection circuit electrically coupled between a first node and a second node. The semiconductor device comprises a discharge circuit electrically coupled between the first node and a third node. The semiconductor device comprises a biasing circuit electrically coupled between the second node and the third node. The discharge circuit and the biasing circuit are configured to electrically conduct the first node and the second node in response to receiving a first signal from the detection circuit through a fourth node. A first voltage difference exists between the third node and the fourth node.