ESD Protection Circuit Layout for Smaller Semiconductor Chips
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Solution Overview
Problem
As the functions of products and the number of separated power supply domains increase, the number of power supply cells (ESD protection circuits) needed also increases, leading to a rise in chip areas due to the larger size of these cells and the increased number of wiring regions.
Innovation Solution
The semiconductor device design places the ESD protection circuit outside the input/output cells and power supply cells, allowing it to be longer in width than in height, thus reducing the overall chip area by minimizing the space occupied by the ESD protection circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of power supply cells (ESD protection circuits) is increased to protect more input/output cells and power supply domains, then the reliability of the semiconductor device is improved, but the chip area increases
Solution Approach 1:
The ESD protection circuit is reoriented from a vertical arrangement (height-oriented) to a horizontal arrangement (width-oriented). By making the circuit extend longer in the width direction rather than the height direction, the patent achieves better ESD protection coverage across multiple power supply domains while consuming less chip area, as the horizontal layout more efficiently utilizes the available space in the IO region.
Solution Approach 2:
The patent employs an asymmetric layout where the ESD protection circuit has different dimensions in the width and height directions, with the width being significantly larger than the height. This asymmetric configuration allows the circuit to cover a broader area in the horizontal direction to protect multiple I/O cells and power supply domains, while minimizing the vertical space occupied, thereby reducing overall chip area usage.
2Reliability
If the ESD protection circuit is placed inside the input/output cells and power supply cells, then the ESD protection is provided, but the chip area increases due to larger cell sizes and increased number of wiring regions
Solution Approach 1:
The ESD protection circuit is extracted from the conventional placement within individual input/output cells and power supply cells, and repositioned to extend horizontally across the IO region. This extraction allows the ESD protection function to cover multiple cells simultaneously without increasing the area of individual cells, thereby reducing overall chip area and simplifying the cell layout while maintaining comprehensive ESD protection.
Data Source
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AI summary
A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.