Integrated ESD Protection Circuit for Low-Capacitance Signal I/O
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration density of semiconductor integrated circuit devices leads to difficulties in rapid signal input/output due to parasitic capacitance in ESD protection circuits, causing signal distortion and hindering efficient static electricity discharge.
Innovation Solution
The semiconductor integrated circuit device incorporates a first protecting unit with serially connected backward diodes and a second protecting unit with forward diodes, integrated in a conductive well without severance, to reduce parasitic capacitance and decrease on-resistance during static electricity input, allowing for effective discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the integration density of ESD protection circuits is increased, then the device size is reduced, but the parasitic capacitance increases causing signal distortion and hindering efficient static electricity discharge
Solution Approach 1:
The ESD protection circuit is divided into multiple protecting units, each containing serially connected backward diodes. This segmentation reduces the parasitic capacitance of each individual unit while maintaining overall protection functionality. The circuit further segments static electricity discharge paths from signal transmission paths, allowing independent optimization of each function.
Solution Approach 2:
The patent extracts the ESD protection function into a dedicated circuit block separate from the main signal processing circuitry. By taking out the protection function and implementing it with specific diode configurations, the design reduces parasitic capacitance impact on signal paths while maintaining comprehensive ESD protection coverage.
2Reliability
If the ESD protection circuit is designed to discharge static electricity efficiently, then the protection capability is improved, but the on-resistance increases affecting signal transmission
Solution Approach 1:
The ESD protection circuit employs dynamic resistance characteristics through parasitic BJT generation. Under normal conditions, the circuit maintains low parasitic capacitance for good signal transmission. When static electricity is detected, the parasitic BJT activates, dynamically switching the circuit to a low on-resistance state for efficient discharge, thus adapting to different operational conditions.
Solution Approach 2:
The patent utilizes parameter changes in the diode configurations and well depths to optimize both protection capability and signal transmission. By adjusting the depth of conductive wells and the arrangement of diodes, the circuit achieves low parasitic capacitance for minimal signal distortion while maintaining sufficient discharge capability through controlled on-resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces parasitic capacitance when no static electricity is present and decreases on-resistance when static electricity is input, enabling efficient signal transmission and discharge while minimizing signal distortion.
Implementation Method 1
When a voltage including a static electricity may be inputted from the pad, a parasitic bipolar junction transistor (BJT) may be generated between the first N-well, the P-well and the second N-well.
Implementation Method 2
When the static electricity may not be inputted from the pad, a parasitic capacitance of the ESD protection circuit may be reduced.
Implementation Method 3
When the static electricity may be inputted from the pad, an on-resistance of the ESD protection circuit may be decreased.
Data Source
AI summary
A semiconductor integrated circuit device may include a first protecting unit and a second protecting unit. The first protecting unit may include first to nth backward diodes serially connected between a pad and a first power line. The second protecting unit may include at least one forward diode connected between the pad and a second power line. The first backward diode and the forward diode connected to the pad may be integrated in one conductive well without a severance to face each other.