ESD Clamp With Tunable Holding Voltage

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Solution Overview

Problem

Existing ESD protection clamps for integrated circuits face challenges in achieving high and tunable holding voltage, low leakage, small silicon area for high current capability, and fast triggering while minimizing capacitance and avoiding temporary or permanent damage during normal operation.

Innovation Solution

The ESD protection device incorporates an ESD clamp with a silicon controlled rectifier (SCR) and a holding voltage tuning circuit, featuring a connection circuit between the cathode and control node, allowing for tunable triggering and high holding voltage during ESD events, while maintaining low leakage and small silicon area usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a low voltage clamp (SCR-based) is used to achieve low clamping voltage and low on-resistance, then ESD protection is improved, but the clamp may trigger during normal operation causing latch up and temporary loss of function

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidnormal operation stability
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the holding voltage of the clamp based on operating conditions. The holding voltage is increased during normal operation to prevent false triggering, and decreased during ESD events to provide effective protection. This is achieved through feedback circuits that monitor current and voltage levels and adjust the clamp's holding voltage accordingly, resolving the contradiction between low clamping voltage and operational stability.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If a high holding voltage clamp (Zener diode or GGNMOS) is used to prevent false triggering, then operational stability is improved, but the clamp fails at low current and has high on-resistance

Engineering Contradiction:
Improveoperational stabilityVSAvoidESD protection capability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies dynamics by making the clamp's holding voltage variable rather than fixed. The holding voltage dynamically adapts to the operating state: it maintains a high value during normal operation to ensure stability, and transitions to a low value during ESD events to provide effective protection. This dynamic adjustment is controlled by feedback mechanisms that detect ESD conditions and modify the clamp's characteristics in real-time, resolving the contradiction between operational stability and ESD protection capability.

Inventive Principle:
Principle #15Dynamics

3Reliability

If conventional ESD clamps are used, then ESD protection is provided, but large chip area is consumed to achieve high current capability

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the holding voltage and other operational parameters of the clamp to optimize its performance for different current levels. This allows a smaller clamp structure to achieve high current capability when needed during ESD events while maintaining low leakage during normal operation, thereby reducing the required chip area while preserving ESD protection capability.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively protects integrated circuits from ESD damage by ensuring high holding voltage and low leakage, preventing temporary or permanent damage during normal operation and ESD events, while optimizing silicon area usage.

Implementation Method 1

The ESD clamp may comprise a silicon controlled rectifier (SCR)

Methodology Applied
Scientific EffectSilicon Controlled Rectifier (SCR) triggering:

Implementation Method 2

The current caused by the avalanching the base-collector junction of the PNP 103 and collector-base junction of the NPN 104

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Implementation Method 3

a holding voltage tuning circuit including a second anode, a second cathode, and a first control node

Methodology Applied
Scientific EffectVoltage tuning:

Data Source

PatentUS10447033B2High holding voltage clamp
Publication Date: 2019.10.15 SOFICS BVBA
  • US10447033B2 patent drawing
  • US10447033B2 patent drawing
  • US10447033B2 patent drawing

AI summary

An electrostatic discharge (ESD) protection device with a high holding voltage is disclosed including at least an ESD clamp coupled to a holding voltage tuning circuit. The ESD clamp may be coupled to the holding voltage tuning circuit through a connection circuit such as a diode. The ESD clamp may be implemented by a first silicon controlled rectifier (SCR) and the holding voltage tuning circuit may be implemented as a second SCR.