ESD Protection Diode String Bias Network

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Solution Overview

Problem

Diode strings used for electrostatic discharge (ESD) protection in integrated circuits (ICs) introduce nonlinear parasitic load characteristics during normal operation, causing undesired loading effects and distortion, especially for high-frequency signals due to amplified parasitic capacitances.

Innovation Solution

A high-speed, high-voltage swing ESD protection scheme is implemented by adding a bias network with resistors and capacitors in parallel with intermediate diodes in the diode string, providing alternative bias current paths to reduce reliance on diode currents for biasing, thus linearizing the load and minimizing parasitic capacitance multiplication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a diode string is used for ESD protection, then protection against excessive voltage and current is provided, but nonlinear parasitic load characteristics are introduced during normal operation

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidnonlinear parasitic load characteristics
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A bias network comprising resistors and capacitors is introduced as an intermediary element coupled to intermediate nodes of the diode string. This bias network provides alternative current paths that linearize the parasitic capacitance multiplication effect, thereby reducing nonlinear load characteristics while preserving the ESD protection function of the diode string.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple diodes are coupled in series for ESD protection, then voltage deviation during normal operation is determined by the number of diodes, but parasitic capacitances are amplified causing loading effects

Engineering Contradiction:
Improvevoltage clamping capabilityVSAvoidparasitic capacitance multiplication
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bias network with resistors and capacitors serves as a mediator that decouples the parasitic capacitance multiplication from the diode string operation. By providing alternative current paths through the bias network, the amplified parasitic capacitances are bypassed, reducing loading effects on driven circuits while maintaining the voltage clamping capability of the multi-diode string.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If diode currents are used for biasing intermediate diodes, then ESD protection is maintained, but stair-step activation occurs causing distortion

Engineering Contradiction:
ImproveESD protection functionVSAvoidlinear load characteristic
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The bias network acts as an intermediary that provides dedicated bias current paths for intermediate diodes through resistors and capacitors. This prevents the stair-step activation phenomenon caused by sequential diode conduction, as the bias network ensures smooth voltage distribution across all diodes. The result is a linearized load characteristic that eliminates distortion during normal operation while preserving ESD protection functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The bias network distributes voltage evenly across diodes, preventing stair-step activation and reducing nonlinear load anomalies, thereby improving the AC load presented to circuitry and preventing distortion during normal operation.

Implementation Method 1

nonlinear parasitic load characteristics during normal operation, causing undesired loading effects and distortion, especially for high-frequency signals due to amplified parasitic capacitances

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS10454268B2System and method of high speed, high voltage swing electrostatic discharge protection
Publication Date: 2019.10.22 SILICON LABORATORIES INC
  • US10454268B2 patent drawing
  • US10454268B2 patent drawing
  • US10454268B2 patent drawing

AI summary

An ESD protection circuit for an IC having multiple diodes coupled in series between a signal pad and a reference pad including a first diode coupled to the signal pad, a last diode coupled to the reference pad, and at least one intermediate diode. The protection circuit includes a bias network which may include one or more resistors, each coupled in parallel with a corresponding intermediate diode. One or more capacitors may be included, each coupled in parallel with a corresponding intermediate diode. For diode strings with four or more diodes, the resistances of the resistors may increase in the direction from the signal pad to the reference pad. The capacitances of the capacitors, if included, may decrease in the direction from the signal pad to the reference pad. The reference pad may be a voltage supply pad, such as a ground pad or a positive supply voltage pad.