Transistor TRIZ Cases

Alternating doped strips in a high voltage semiconductor device create a full depletion region to protect integrated MOS transistors.

Notches in active pillars extend electron migration paths to reduce electric leakage between adjacent pillars.

An ESD protection circuit uses a detection unit and voltage-controlled switch to divert currents, reducing vulnerability in scaled ICs.

A floating gate memory structure integrates a ferroelectric dipole layer to enable Fowler-Nordheim tunneling and electric potential switching.

Doped substrate and buried oxide layers stabilize epitaxial silicon growth on FinFET fins, resolving thickness inconsistency across wafers.

Segmented trench gate fins reduce channel resistance in miniaturized DRAM cells while preventing operational interference between adjacent transistors.

A monolithic microwave integrated circuit uses a high resistivity semiconductor substrate to minimize parasitic resistance in passive components.

Atomic layer deposition of germanium using amidinate precursors creates conformal films on semiconductor substrates.

Alternating conductivity pillars in superjunction structures optimize charge balance to enhance breakdown voltage while maintaining low on-resistance.

A semiconductor device stacks logic and memory circuits separated by an insulating layer to enable direct electrical connections between the components.

A first oxygen provider layer on a barrier substrate supplies oxygen to an oxide semiconductor film, preventing oxygen vacancies and maintaining film quality.

Dual lateral thyristors dissipate overvoltages via optimized doping profiles.

A planar bottom electrode structure uses vertical receiving rooms to accommodate dielectric and plate electrodes within a compact footprint.

An electrostatic discharge protection circuit uses an annular well region to increase substrate bias and ensure complete transistor activation.

Sacrificial spacer elements define reduced bottom widths in metal lines while maintaining wider top sections for reliable via connections.

A gated graphene component uses a backgate region to bias contact field regions.

Side wing contacts eliminate etch stop layer contact holes, reducing channel length and improving ion current in oxide thin film transistors.

A unified fabrication method forms vertical-transport and planar field-effect transistors on a single substrate using shared gate electrodes.

Etch stop layers guide selective removal processes to control capacitor length variations and ensure reliable active layer connections.

A double-sided semiconductor package integrates passive components into the lower carrier substrate to enhance electrical connectivity.

Selective epitaxial lateral overgrowth creates a planar capping layer on finFETs, reducing contact resistance while managing manufacturing complexity.

Shifted openings in the gate-bottom protection region reduce electric field strength and on-resistance while enhancing short-circuit tolerance.

Selective epitaxial growth and ion doping modify fin structures to enhance carrier mobility, suppressing short-channel effects in scaled FinFETs.

An indented p-n junction interface expands the contact area within a CMOS image sensor photodiode structure to increase full well capacity.

Applying specific back gate voltage to amorphous oxide semiconductor transistors modulates carrier density and reduces threshold variation.

An auxiliary trench enables precise source region doping while optimizing channel width to reduce on-resistance and improve breakdown voltage.

A flash memory programming circuit applies dynamic control gate voltage to enhance hot electron injection efficiency.

Segmented source/drain doping regions with conductive layers reduce parallel resistance, enabling more gate structures to operate under constant voltage.

A five-transistor pixel circuit uses correlated double sampling to manage photodiode operation modes.

A vertical one-time programmable fuse structure reduces silicon footprint by orienting conductive layers within an insulating opening.

Movable mask segments rough etching from precise finishing, resolving the contradiction between working speed and manufacturing precision.

A graphene light-emitting device uses doped layers and a moiré superlattice to emit light through electro-photoluminescence.

Vertical integration of antifuses using a buried oxide dielectric reduces circuit area while maintaining programming efficiency.

PMOSFET and tri-state inverter provide over-voltage protection while minimizing quiescent supply current.

An anthracene derivative compound enables high mobility semiconductor devices via wet film forming methods.

A substrate resistor structure uses filler removal to define precise resistance values through controlled material thickness.

A multiplexer adjusts source driver signal strength across sectoral leads to ensure uniform display output.

Segmented substrates resolve epitaxial layer height variations while maintaining single crystal silicon quality across the memory device.

Adjusting titanium and nitrogen content in TiN gates tunes work functions for low threshold voltages while preventing metal etching failures.

Resistors and capacitors in the bias network distribute voltage across diodes, reducing nonlinear parasitic load characteristics.

Segmented gate structures resolve the trade-off between high temperature durability and operating speed by combining polysilicon and metal materials.

Vertical gate extension blocks backlight incidence on the channel layer, resolving reliability degradation in optical touch screens.

A memory device stacks cell arrays with alternating bit line pairs to equalize parasitic capacitance values.

SiGe source and drain structures induce mechanical strain in transistor channels to enhance carrier mobility.

Graphene field-effect transistor arrays detect nucleic acid sequences via electrical conductivity changes.

A semiconductor device generates voltage information signals from primary side voltage using comparators and current generation circuits.

A suspended fin gate-all-around transistor structure integrates with bulk silicon substrates using a dedicated isolation dielectric layer.

Graded doping layers suppress short channel effects in thin film transistors, enabling high-resolution displays without increasing unit pixel size.