Integrating Vertical-Transport and Planar Transistors on Single Substrate
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Solution Overview
Problem
Existing semiconductor device fabrication methods struggle to efficiently integrate vertical-transport field-effect transistors and planar field-effect transistors on the same substrate, as they require decoupling of gate lengths and dielectric thicknesses, which is challenging with traditional fabrication processes.
Innovation Solution
A method is developed to form vertical-transport field-effect transistors and planar field-effect transistors on the same substrate by using sacrificial fins and semiconductor fins, with concurrently formed gate electrodes and dielectric layers of equal thickness, allowing for independent gate length control and flexible integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional fabrication processes are used to integrate vertical-transport and planar field-effect transistors, then the transistors can be formed on the same substrate, but the gate lengths and dielectric thicknesses must be decoupled which complicates the fabrication process
Solution Approach 1:
The patent merges the fabrication processes for vertical-transport and planar field-effect transistors into a single unified process. Both transistor types share common fabrication steps including gate electrode formation, dielectric layer deposition, and patterning operations, eliminating the need for separate decoupled processes while maintaining independent gate length control through selective fin removal
Solution Approach 2:
The fabrication process is designed to be universal, handling both vertical-transport and planar transistor configurations through the same sequence of operations. The process uses a single gate electrode layer, single dielectric stack, and common lithography/etching steps that can produce either transistor type depending on the fin configuration, thereby reducing overall process complexity
2Manufacturing precision
If separate fabrication processes are used for vertical-transport and planar field-effect transistors, then each transistor type can be optimized independently, but the fabrication time and process steps increase
Solution Approach 1:
The unified fabrication process is segmented into common steps and transistor-specific steps. Common steps (gate electrode formation, dielectric deposition, initial patterning) are shared by both transistor types, while transistor-specific outcomes are achieved through selective fin removal and targeted etching operations, allowing independent optimization without requiring separate full fabrication sequences
Solution Approach 2:
The process performs preliminary actions that benefit both transistor types simultaneously, such as forming a single gate electrode layer and dielectric stack that serve both vertical-transport and planar transistors. The sacrificial fins are formed in advance and can be selectively removed later, allowing the common structure to be prepared once while enabling subsequent independent optimization
Data Source
AI summary
Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed.