Monolithic Microwave Integrated Circuits Using High Resistivity Substrates
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Solution Overview
Problem
Conventional approaches for forming monolithic integrated circuits capable of operating at microwave frequencies face challenges due to degraded quality factors in passive components and adverse interactions between planar inductors and the semiconductor substrate, leading to unsatisfactory performance.
Innovation Solution
The solution involves forming both active and passive elements on a common semiconductor substrate using planar integrated circuit processing technology, with high resistivity substrate and through-substrate vias to minimize parasitic coupling and resistance, enabling the creation of a monolithic microwave integrated circuit with improved Q factors and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional approaches are used to form monolithic integrated circuits at microwave frequencies, then manufacturing simplicity is maintained, but quality factor of passive components degrades and performance becomes unsatisfactory
Solution Approach 1:
The patent segments the monolithic substrate into distinct functional regions: active device regions for transistors and separate passive component regions for inductors and capacitors. This spatial segmentation allows each component type to be optimized independently while maintaining monolithic integration, resolving the contradiction between performance and manufacturing simplicity.
Solution Approach 2:
The patent applies local quality by using high-resistivity substrate material specifically in the passive component regions to minimize parasitic coupling, while maintaining standard substrate properties in active device regions. This localized optimization improves passive component Q-factors without complicating the overall manufacturing process.
2Productivity
If planar inductors are formed on the semiconductor substrate, then monolithic integration is achieved, but parasitic coupling between inductors and substrate increases
Solution Approach 1:
The patent introduces an intermediary high-resistivity substrate layer between the planar inductors and the conductive semiconductor substrate. This intermediary layer acts as a mediator that maintains the monolithic integration structure while blocking parasitic coupling paths, allowing inductors to be formed directly on the substrate without degradation.
Solution Approach 2:
The patent changes the electrical resistance parameter of the substrate in specific regions by using high-resistivity material. This parameter change reduces the parasitic coupling between planar inductors and the substrate, enabling monolithic integration to proceed without the harmful side effects of substrate interaction.
3Reliability
If separately produced passive and active elements are assembled, then satisfactory performance is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges separately produced passive and active elements into a single monolithic structure by forming both types of components directly on the same semiconductor substrate using compatible processing steps. This combining eliminates the need for separate assembly operations while maintaining the performance benefits of optimized component designs.
Data Source
AI summary
Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.