Planar Bottom Electrode Fabrication via Vertical Receiving Rooms
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Solution Overview
Problem
Concave type capacitors face manufacturing limitations due to insufficient space for bottom electrodes, dielectrics, and plate electrodes as feature sizes decrease, leading to increased current leakage and reduced capacitance in semiconductor devices.
Innovation Solution
A method involving the formation of a sacrificial layer structure with trenches filled by insulating and electrode materials, creating receiving rooms between insulating and electrode layers, allowing for sufficient space for dielectrics and plate electrodes, which involves defining first and second trenches in a sacrificial layer structure, filling them with insulating and electrode materials, and removing the sacrificial layer to define receiving rooms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If concave type capacitor structure is used, then manufacturing process is simpler, but insufficient space is available for bottom electrodes, dielectrics and plate electrodes when feature size is reduced
Solution Approach 1:
The patent transitions from a conventional planar capacitor structure to a three-dimensional stacked structure by forming receiving rooms vertically in the substrate. Multiple capacitor units are stacked in the vertical direction, with bottom electrodes, dielectrics, and plate electrodes arranged in alternating layers within the receiving rooms, thereby increasing the available volume for capacitor components without increasing the planar footprint.
Solution Approach 2:
The patent implements a nested structure where multiple capacitor units are stacked within vertically extended receiving rooms. Each receiving room contains nested layers of bottom electrodes, dielectrics, and plate electrodes, with upper receiving rooms positioned above lower receiving rooms, creating a compact three-dimensional arrangement that maximizes space utilization.
2Productivity
If feature size is reduced to meet integration demands, then device integration is improved, but space for bottom electrodes, dielectrics and plate electrodes becomes insufficient
Solution Approach 1:
The patent resolves the space limitation by extending the capacitor structure into the vertical dimension. Receiving rooms are formed vertically in the substrate, and capacitor components are arranged in stacked layers within these vertical receiving rooms, allowing increased component volume without increasing the planar feature size.
Solution Approach 2:
The patent changes the spatial arrangement parameter from two-dimensional planar layout to three-dimensional vertical stacking. By forming receiving rooms that extend vertically into the substrate and arranging capacitor units in stacked configurations, the available volume for capacitor components is increased while maintaining small planar feature sizes for high integration.
3Reliability
If thicker dielectrics are deposited to reduce current leakage, then capacitance is improved, but more space is required in the capacitor structure
Solution Approach 1:
The patent accommodates thicker dielectric layers by utilizing the vertical dimension of the receiving rooms. Dielectric layers are deposited within the vertically extended receiving rooms, allowing increased dielectric thickness without increasing the planar footprint of the capacitor structure.
Solution Approach 2:
The patent nests multiple dielectric layers within the vertical receiving rooms, alternating with bottom electrode layers and plate electrode layers. This nested arrangement allows thick dielectric layers to be incorporated while maintaining a compact overall structure that fits within the substrate volume.
Data Source
AI summary
A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.