Memory Device Asymmetric Bit Line Noise Reduction
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Solution Overview
Problem
Highly integrated memory devices with open bit-line configurations face challenges in reducing noise interference, achieving high reliability, and low power consumption, as existing methods like the twisted bit-line method are not applicable to these configurations.
Innovation Solution
A memory device design featuring overlapping cell arrays with alternately provided bit line pairs, where at least one bit line pair is a twisted bit line pair, allowing for reduced noise interference and enhanced reliability by equalizing parasitic capacitance values between bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If open bit-line configuration is used for high integration, then memory device integration is improved, but noise interference increases
Solution Approach 1:
The patent applies asymmetry by implementing a folded bit-line configuration where bit lines are arranged in an asymmetric pattern with alternating connections to memory cell columns. This asymmetric arrangement reduces noise interference by preventing uniform noise propagation across all bit lines, while still achieving high integration density through the folded layout approach.
Solution Approach 2:
The patent transitions from a planar open bit-line configuration to a three-dimensional folded bit-line structure. By folding the bit lines and routing them through multiple layers and dimensions, the design achieves high integration while spatially separating noise sources from sensitive memory cells, thereby reducing noise interference through dimensional separation.
2Object-affected harmful factors
If twisted bit-line method is applied, then noise reduction is improved, but device complexity increases
Solution Approach 1:
The patent segments the bit-line configuration into distinct folded sections, each handling specific memory cell columns. By dividing the bit-line network into manageable segments with standardized folding patterns, the design reduces noise through systematic arrangement while keeping individual segment complexity low and reusable across the memory array.
Solution Approach 2:
The folded bit-line configuration serves multiple functions simultaneously: it achieves noise reduction through spatial separation, maintains high integration density through compact folding, and provides standardized reusable patterns across memory arrays. This multi-functionality reduces overall device complexity by using a single versatile configuration approach for multiple design requirements.
Data Source
AI summary
A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are stacked. One of two bit lines of a first bit line pair is electrically connected to A memory cells of the first cell array, and the other of the two bit lines of the first bit line pair is electrically connected to D memory cells of the second cell array. One of two bit lines of a second bit line pair is electrically connected to B memory cells of the first cell array and F memory cells of the second cell array, and the other of the two bit lines of the second bit line pair is electrically connected to C memory cells of the first cell array and E memory cells of the second cell array. The first bit line pairs and the second bit line pairs are alternately provided.