FinFET Gate Control via Selective Epitaxy and Ion Doping
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Solution Overview
Problem
As semiconductor feature dimensions decrease, the control ability of the gate over the channel in MOSFETs deteriorates, leading to increased subthreshold leakage and short-channel effects, which are mitigated in FinFETs but require improved electrical performance.
Innovation Solution
A method for fabricating a semiconductor structure involving discrete fins with a gate structure covering top and sidewall surfaces, and forming pull-up and pull-down doped epitaxial layers and regions on both sides of the gate, using in-situ doped selective epitaxial processes and ion doping to enhance carrier mobility and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length of MOSFET decreases to accommodate reduction of feature dimensions, then the device can fit smaller features, but the gate control ability over the channel deteriorates and subthreshold leakage increases
Solution Approach 1:
The patent transitions from planar MOSFET to FinFET structure, adding vertical dimension to the channel. The gate wraps around the fin from multiple sides (top and sidewalls), providing three-dimensional control over the channel instead of planar control, which significantly improves gate control ability despite reduced feature dimensions
Solution Approach 2:
The channel is segmented into multiple fins rather than a single planar channel. Each fin provides an independent pathway controlled by the gate, allowing better overall control while maintaining current flow. The source and drain are also segmented across multiple fins
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach improves carrier mobility and reduces contact resistance, effectively suppressing short-channel effects and enhancing the electrical performance of FinFETs by providing stronger gate control and larger volume doped epitaxial layers.
Implementation Method 1
forming pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region
Implementation Method 2
an in-situ doped selective epitaxial process, including: forming pull-up epitaxial layers in the fin on both sides of the gate structure in the pull-up transistor region, and in-situ self-doping P-type ions during the process for forming the pull-up epitaxial layers
Implementation Method 3
An epitaxial layer is not formed when forming the second pull-down doped region and an ion doping process is directly performed on the fin
Data Source
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AI summary
A semiconductor structure, a method for fabricating the semiconductor structure and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pull-up transistor region and a pull-down transistor region. The method also includes forming a gate structure on each fin; and forming pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region. In addition, the method includes forming a first pull-down doped region connected to an adjacent pull-up doped epitaxial layer in the fin on one side of the gate structure in the pull-down transistor region. Further, the method includes forming a second pull-down doped region by performing an ion-doped non-epitaxial layer process on the fin on another side of the gate structure in the pull-down transistor region.