Double-Sided Semiconductor Package Cooling and Passive Component Integration
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Solution Overview
Problem
Semiconductor packages used in high-current electrical circuits, such as motor vehicle inverters, face challenges in achieving sufficient cooling, low impedance, and minimizing leakage inductances, which limits their performance.
Innovation Solution
A semiconductor package with a double-sided cooling structure is developed, comprising an upper electrically conductive element, a lower carrier substrate with an insulating layer, electrically conductive spacers, power semiconductor chips, and a passive electrical component, where the spacers and passive components are strategically positioned to enhance cooling and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a conventional single-sided cooling structure is used, then the device complexity is low, but the heat dissipation performance is insufficient
Solution Approach 1:
The cooling structure is segmented into two separate cooling surfaces: an upper cooling surface on the upper electrically conductive element and a lower cooling surface on the lower carrier substrate. This segmentation allows independent optimization of each cooling surface and enables simultaneous cooling from both sides, effectively resolving the contradiction between heat dissipation performance and structural complexity
Solution Approach 2:
The cooling approach transitions from single-sided (one-dimensional) to double-sided (two-dimensional) cooling by utilizing both the upper and lower surfaces of the semiconductor package. This dimensional expansion doubles the effective cooling area and improves heat dissipation performance without proportionally increasing structural complexity
2Reliability
If passive electrical components are integrated within the package, then the electrical connectivity and impedance are improved, but the device complexity increases
Solution Approach 1:
Passive electrical components are merged with the lower carrier substrate, forming an integrated assembly where the substrate serves both as a mechanical support and as an electrical interconnection structure. This merging reduces the number of separate components and improves electrical connectivity while minimizing the increase in device complexity
Solution Approach 2:
The lower carrier substrate is designed to serve multiple functions simultaneously: it provides mechanical support for the semiconductor chips, acts as a lower cooling surface, and integrates passive electrical components for electrical interconnection. This multi-functionality improves electrical connectivity without requiring additional dedicated structures, thereby limiting the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double-sided cooling structure and strategic placement of passive components improve heat dissipation and electrical efficiency, enhancing the performance of semiconductor packages by reducing impedance and leakage inductances, thereby increasing the performance of high-current circuits like motor vehicle inverters.
Implementation Method 1
a double-sided cooling structure, the semiconductor package comprising an upper electrically conductive element... a lower carrier substrate... improve heat dissipation
Data Source
AI summary
A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer with an outwardly exposed surface and an electrical insulating layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip, and a passive electrical component electrically connected to the upper electrically conductive layer of the lower carrier substrate.