Trench Gate Fin Transistor for DRAM Channel Resistance

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Solution Overview

Problem

Miniaturization of DRAM semiconductor devices leads to increased channel resistance, operational interference between transistors, and manufacturing difficulties due to trench gate arrangements, resulting in insufficient ON current and reliability issues.

Innovation Solution

A semiconductor device design featuring gate electrode trenches with fins protruding from the bottom, a specific thickness distribution of the gate insulating film, and impurity diffusion regions to form channel regions on fewer surfaces, reducing channel resistance and preventing operational interference between adjacent transistors, while allowing for independent operation and easier manufacturing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the transistor gate length is reduced to miniaturize DRAM, then the cell size is reduced, but the short channel effect increases causing increased subthreshold current and reduced threshold voltage

Engineering Contradiction:
Improvecell sizeVSAvoidthreshold voltage stability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The gate structure is segmented into a recessed gate portion embedded in the semiconductor substrate and a projected gate portion extending above the surface. This segmentation allows the gate length to be extended in the vertical direction while maintaining a small cell footprint, thereby reducing the short channel effect and improving threshold voltage stability without sacrificing miniaturization benefits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate electrode is extended into the vertical dimension by creating a recessed gate structure that penetrates into the substrate. This dimensional change allows the effective gate length to be increased without increasing the planar cell area, thus maintaining threshold voltage control in miniaturized devices.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the impurity concentration in the semiconductor substrate is increased to suppress threshold voltage drop, then the threshold voltage stability is improved, but the joint leak current increases

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidjoint leak current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The gate insulating film is designed with non-uniform thickness, being thicker at the interface with the semiconductor substrate and thinner toward the gate electrode. This local quality variation allows for better electrical control at the critical substrate interface while managing the overall gate structure properties, improving threshold voltage stability without requiring excessive impurity concentration that would increase leak current.

Inventive Principle:
Principle #3Local quality

3Reliability

If a trench-gate transistor is used to ensure sufficient effective channel length, then the threshold voltage control is improved, but the channel resistance increases due to channel region formed on three surfaces

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidchannel resistance
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The gate structure is divided into recessed and projected portions, with the channel region primarily formed on the bottom surface of the recessed gate rather than on all three surfaces. This segmentation reduces the channel formation area, thereby lowering channel resistance while maintaining sufficient effective channel length through the vertical extension of the gate electrode for proper threshold voltage control.

Inventive Principle:
Principle #1Segmentation

4Productivity

If the trench gate arrangement pitch is reduced to increase device density, then the cell density is improved, but operational interference between adjacent transistors occurs

Engineering Contradiction:
Improvedevice densityVSAvoidtransistor operation independence
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By extending the gate electrode vertically into the substrate, the effective gate length is increased without increasing the horizontal pitch between gates. This dimensional change allows adjacent transistors to be placed closer together while maintaining sufficient electrical isolation, thus increasing device density without causing operational interference.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

5Reliability

If the gate electrode projects above the substrate surface to form a trench-gate structure, then the gate control is improved, but the formation of bit wiring and capacitor becomes extremely difficult

Engineering Contradiction:
Improvegate controlVSAvoidwiring and capacitor formation
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The gate electrode projects above the substrate surface only partially, with the projected portion having a controlled height that provides sufficient gate control while not excessively interfering with subsequent manufacturing steps. This partial projection achieves the necessary electrical control while allowing bit wiring and capacitor formation to proceed with reasonable ease.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9236387B2Semiconductor device and manufacturing method thereof
Publication Date: 2016.01.12 LONGITUDE LICENSING LTD
  • US9236387B2 patent drawing
  • US9236387B2 patent drawing
  • US9236387B2 patent drawing

AI summary

A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face.