Gated Graphene Device With Independent Backgate Control

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Solution Overview

Problem

Existing microelectronic devices with graphene components face challenges in independently controlling carrier density in the channel region and under the contacts, leading to increased parasitic resistance.

Innovation Solution

A microelectronic device design featuring a gated graphene component with a graphitic layer over a semiconductor material, including a backgate region and contact field regions of opposite conductivity types, allowing independent biasing to control carrier densities and reduce resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a graphitic layer with metal contacts and channel region is used, then the device can operate as a gated graphene component, but independent control of carrier density under contacts and in channel region cannot be achieved

Engineering Contradiction:
Improveindependent carrier density controlVSAvoidstructure complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The device structure is segmented into distinct functional regions: a channel region with a gate for carrier density modulation, and separate contact regions with backgate control for maintaining high carrier density. This spatial segmentation allows independent control of carrier density in different regions of the graphitic layer, resolving the contradiction between operational control and structural simplicity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the device are assigned different functional qualities: the channel region is optimized for carrier density modulation via top gate control, while the contact regions are optimized for high carrier density maintenance via backgate control. This local differentiation of functional properties enables independent carrier density control without requiring a completely complex restructured device architecture.

Inventive Principle:
Principle #3Local quality

2Productivity

If carrier density in channel region is modulated for device operation, then the device can be controlled, but carrier density under contacts decreases leading to increased parasitic resistance

Engineering Contradiction:
Improvedevice control capabilityVSAvoidparasitic resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The control mechanism is extended from a single top gate to include both top gate and backgate dimensions. The top gate controls carrier density in the channel region for device operation, while the backgate simultaneously controls carrier density in the contact regions. This dimensional extension of control allows independent optimization of both device control capability and parasitic resistance without trade-offs.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The backgate acts as an intermediary control element that specifically targets the contact regions to maintain high carrier density independently of the channel region control. This intermediary structure enables the contact regions to maintain optimal electrical properties even when the channel region carrier density is modulated for device operation, thereby reducing parasitic resistance while preserving device control capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11296237B2Integration of graphene and boron nitride hetero-structure device over semiconductor layer
Publication Date: 2022.04.05 TEXAS INSTRUMENTS INC
  • US11296237B2 patent drawing
  • US11296237B2 patent drawing
  • US11296237B2 patent drawing

AI summary

A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.