Vertical OTP Fuse Structure for High Density Memory
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Solution Overview
Problem
Existing semiconductor devices with lateral one-time-programmable (OTP) fuses face space constraints due to their planar orientation, which increases the area required for OTP memory and adds cost, especially in area-sensitive applications.
Innovation Solution
The development of a vertical OTP fuse structure over a PN junction, where a conductive layer is formed vertically within an insulating layer, allowing for a higher density layout and reduced silicon area usage by orienting the fuse vertically, thereby minimizing space and enhancing fuse density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lateral OTP fuse structure is used, then fuse functionality is achieved, but silicon area consumption increases
Solution Approach 1:
The patent transitions from a lateral (planar) fuse structure to a vertical (three-dimensional) fuse structure. The conductive layer extends vertically through the insulating layer rather than laterally across the substrate, utilizing the third dimension (height/depth) to achieve the same electrical functionality while minimizing footprint area. This dimensional change allows the fuse to maintain its programming and reading capabilities while occupying significantly less silicon surface area.
2Productivity
If fuse density is increased, then area efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The fuse structure is segmented into distinct vertical layers: an insulating layer and a conductive layer embedded within it. This segmentation allows for standardized fabrication processes where each layer can be formed independently using conventional semiconductor manufacturing techniques. The modular layered structure simplifies the manufacturing complexity while enabling high density, as the same fabrication steps can be repeated across the wafer to create numerous fuses in parallel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical OTP fuse design significantly reduces the silicon area required, achieving a higher density of fuses per unit area and lowering the overall cost by minimizing the space needed for OTP memory, while maintaining the ability to program and read the fuses effectively.
Implementation Method 1
The large electric current used for programming an OTP fuse is initially carried mostly by the silicide layer, which causes the silicide layer to heat to a temperature that melts and diffuses a portion of the silicide material into the polysilicon
Implementation Method 2
The silicide layer to heat to a temperature that melts and diffuses a portion of the silicide material into the polysilicon
Implementation Method 3
The current is then carried predominately by the fuse body as the silicide and dopant atoms drift or migrate to one end of the fuse
Data Source
AI summary
A vertical OTP fuse formed in a semiconductor device has a substrate and an insulating layer formed over the substrate with an opening through the insulating layer extending to the substrate. A conductive layer, such as silicide, is formed over a sidewall of the opening. A resistive material, such as polysilicon, is deposited within the opening over the first conductive layer to form a first vertical OTP fuse. A plurality of vertical OTP fuses can be arranged in an array. A PN junction diode or transistor is formed in the substrate aligned with the first vertical OTP fuse. A second conductive layer is formed over the first vertical OTP fuse. The first vertical OTP fuse can be disposed between the second conductive layer and a third conductive layer. A second vertical OTP fuse can be formed over the first vertical OTP fuse for redundancy.