Lateral Thyristor ESD Protection with Zener Triggering

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Solution Overview

Problem

Existing devices for protecting electronic circuits against electrostatic discharges using lateral thyristors have inefficiencies, such as delayed triggering due to parasitic currents, which increase the time required to activate the protection mechanism.

Innovation Solution

A device comprising a semiconductor substrate with specific conductivity types, buried regions, and lateral thyristors, along with stop channel regions and insulating walls, is designed to efficiently dissipate overvoltages by optimizing the doping levels and structural layout to reduce parasitic currents and enhance triggering speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional lateral thyristor structures are used for electrostatic discharge protection, then the device can dissipate overvoltages, but the triggering is delayed due to parasitic currents

Engineering Contradiction:
Improveprotection effectivenessVSAvoidtriggering time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The device is divided into two separate lateral thyristors (first and second lateral thyristors) with distinct well structures, allowing independent optimization of each thyristor's triggering characteristics and reducing mutual interference from parasitic currents

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different doping levels are applied to specific regions: the first and second wells have a first doping level, the second and third regions have a second doping level, and the semiconductor layer has a third doping level. This local differentiation optimizes carrier injection and reduces parasitic currents in critical areas, enabling faster triggering

Inventive Principle:
Principle #3Local quality

2Speed

If the doping levels in wells and regions are increased to reduce parasitic currents, then triggering speed improves, but device complexity increases

Engineering Contradiction:
Improvetriggering speedVSAvoiddoping structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The first and second wells are formed in the same semiconductor layer on the substrate, sharing common structural elements and fabrication processes. This merging approach reduces overall device complexity while maintaining the benefits of multiple doped regions for fast triggering

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If additional regions and wells are added to form lateral thyristors, then protection capability improves, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrostatic discharge protectionVSAvoidfabrication simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The semiconductor layer serves multiple functions: it acts as the active region for both lateral thyristors, provides the substrate for well formation, and enables the PNPN junction structures. This multi-functionality reduces the number of separate manufacturing steps required

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The lateral thyristors are formed by creating wells and regions within the vertical thickness of the semiconductor layer, utilizing the third dimension (depth) to establish complex PNPN junctions without requiring additional lateral expansion or separate layers, thus simplifying fabrication

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces the time needed to activate the protection mechanism, improving the device's responsiveness to electrostatic discharges and enhancing its ability to dissipate overvoltages efficiently.

Implementation Method 1

the first buried region forms with the substrate a PN junction defining a Zener diode, the avalanche voltage of the first Zener diode determining the triggering threshold of the protection device

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS11437365B2Device of protection against electrostatic discharges
Publication Date: 2022.09.06 STMICROELECTRONICS (TOURS) SAS
  • US11437365B2 patent drawing
  • US11437365B2 patent drawing
  • US11437365B2 patent drawing

AI summary

A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.