HK/MG Compatible Floating Gate Memory With Ferroelectric Dipole
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Solution Overview
Problem
Conventional nanocrystal-based non-volatile memory devices face compatibility issues with high dielectric constant/metal gate processes and suffer from charge loss due to degradation, limiting further scaling and device density.
Innovation Solution
The development of high dielectric constant/metal gate compatible floating gate/ferroelectric dipole non-volatile memory and logic devices, utilizing a metal gate, oxide layer, and nitride caps, which enable programming and erasing through Fowler-Nordheim tunneling or electric potential dipole switching, allowing for increased device density and compatibility with HK/MG processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional nanocrystal-based non-volatile memory devices are used, then device density can be improved, but compatibility with high dielectric constant/metal gate processes deteriorates
Solution Approach 1:
The patent changes the material parameters and operational mechanisms of the memory device by replacing nanocrystal-based FN tunneling with a floating gate structure that supports both FN tunneling and electric potential dipole switching. This allows the device to maintain high density while being compatible with HK/MG fabrication processes, as the floating gate can be formed using standard HK/MG process steps.
Solution Approach 2:
The patent employs a composite structure combining floating gate material with ferroelectric dipole layer, creating a hybrid memory cell that integrates the advantages of both approaches. The floating gate provides stable charge storage compatible with HK/MG processes, while the ferroelectric dipole enables low-power read operations and enhanced retention, achieving both density and process compatibility.
2Ease of operation
If conventional nanocrystal-based non-volatile memory devices are used, then programming capability is achieved, but charge loss due to degradation occurs
Solution Approach 1:
The patent changes the charge storage mechanism from nanocrystal trap states to a floating gate structure that can store charge more reliably. The floating gate, being a continuous conductive layer, provides better charge confinement and reduced leakage compared to discrete nanocrystals, thereby improving charge retention while maintaining programming capability through FN tunneling.
Solution Approach 2:
The patent replaces the fragile nanocrystal structure with a more robust floating gate that does not degrade as quickly. The floating gate structure is more tolerant of fabrication variations and operational stress, providing long-term reliability without requiring the delicate nanocrystal formation processes.
3Length of moving object
If nanocrystals are implemented to reduce tunnel oxide thickness, then device scaling is enabled, but further scaling is limited by process constraints
Solution Approach 1:
The patent changes the approach to thin tunnel oxide from nanocrystal insertion to direct floating gate formation over the oxide. This allows the tunnel oxide to be made extremely thin using standard HK/MG atomic layer deposition (ALD) processes, enabling further scaling. The floating gate can be formed conformally over the thin oxide without requiring nanocrystal self-assembly or insertion steps that limit scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances device density and compatibility with HK/MG processes, addressing charge loss and degradation issues, enabling further scaling and efficient data storage operations.
Implementation Method 1
the floating gate is operable to be programmed or erased by a Fowler-Nordheim (FN) tunneling operation
Implementation Method 2
the oxide layer is operable to be programmed or erased by an electric potential dipole switching operation
Data Source
AI summary
Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a nonvolatile memory device.