3D Memory Substrate Segmentation for Integration Density
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration density while maintaining effective transistor characteristics, particularly due to variations in epitaxial layer heights and gate electrode deterioration when forming cell and peripheral circuit regions in different directions perpendicular to a substrate.
Innovation Solution
The memory device configuration includes a peripheral circuit region on a first substrate and a cell region on a second substrate, with both substrates forming a single substrate of single crystal silicon, where the second substrate is formed by single-crystallizing an amorphous silicon layer extending from the first substrate, and a high-density plasma oxide film is used to fill the space between the substrates, enhancing integration and reducing epitaxial layer deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell region and peripheral circuit region are formed in different directions perpendicular to substrate, then integration density is improved, but epitaxial layer height variations occur
Solution Approach 1:
The substrate is divided into two separate regions: a first substrate for peripheral circuit elements and a second substrate for memory cell elements. This segmentation allows independent optimization of each region while maintaining overall integration, resolving the contradiction between high integration density and manufacturing precision by treating the two functional areas as distinct but connected substrates.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional integration by stacking the first and second substrates vertically. The first substrate is disposed below the second substrate in a direction perpendicular to their surfaces, enabling cell and peripheral circuit regions to coexist in different spatial dimensions, thereby achieving high integration density without compromising epitaxial layer uniformity within each substrate.
2Quantity of substance
If cell region and peripheral circuit region are formed in different directions perpendicular to substrate, then integration density is improved, but gate electrode deterioration occurs
Solution Approach 1:
By segmenting the device into separate first and second substrates, each with its own gate electrode structures optimized for specific functions, the patent prevents gate electrode deterioration. The first substrate contains peripheral circuit gate electrodes while the second substrate contains memory cell gate electrodes, allowing independent optimization and protection of each gate electrode system.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the first and second substrates. This insulating layer, disposed between the substrates, provides electrical isolation and mechanical support, preventing harmful interactions between the two substrate systems while maintaining their vertical integration, thereby protecting gate electrode characteristics from deterioration.
3Reliability
If second substrate is formed by single-crystallizing amorphous silicon layer, then single crystal silicon quality is maintained, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming an amorphous silicon layer on the first substrate before performing selective single-crystallization. This pre-preparation step establishes the foundation for subsequent crystal growth, allowing the second substrate to be formed with high single crystal quality through a controlled solid-phase epitaxial process, thereby managing manufacturing complexity through staged processing.
Solution Approach 2:
The patent utilizes phase transitions by transforming amorphous silicon into single crystal silicon through solid-phase epitaxial growth. The amorphous silicon layer serves as a precursor that undergoes phase transition to crystalline structure when subjected to thermal processing, enabling the formation of high-quality single crystal second substrate while managing process complexity through controlled phase change.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integration density of memory devices, reduces epitaxial layer height variations, and improves the operational characteristics of memory cells by maintaining single crystal silicon quality across both substrates, thereby improving overall device performance.
Implementation Method 1
the second substrate is formed by single-crystallizing an amorphous silicon layer extending from the first substrate
Implementation Method 2
a high-density plasma oxide film is used to fill the space between the substrates
Data Source
AI summary
There is provided a peripheral circuit region including a plurality of circuit elements disposed on a first substrate; and a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, and a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region, wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate.