Stacked Semiconductor Logic and Memory Circuits
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Solution Overview
Problem
Current semiconductor devices face increased processing time and power consumption due to the integration of logic and memory circuits on the same substrate, leading to slower operation speeds and larger device sizes.
Innovation Solution
A semiconductor device design featuring a memory circuit and a logic circuit separated by an insulating layer, where the logic circuit is electrically connected to the memory circuit, allowing for independent operation and reducing the need for logic processing in the central processing unit, thereby enhancing speed and reducing size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If logic circuit and memory circuit are formed over the same substrate, then integration is achieved, but the area of the integrated circuit is increased and operation speed is decreased
Solution Approach 1:
The patent applies three-dimensional stacking to separate logic and memory circuits into different layers (first circuit and second circuit) with an insulating layer therebetween. This vertical arrangement allows both circuits to coexist on the same substrate without increasing planar area, while reducing interconnect length to improve operation speed.
Solution Approach 2:
The logic circuit and memory circuit are nested in a stacked configuration where one circuit is positioned over the other. The second circuit includes a region overlapping with the first circuit, creating a compact integrated structure that reduces overall device area while maintaining functional separation.
2Device complexity
If logic circuit and memory circuit are formed over the same substrate, then integration is achieved, but the area of the integrated circuit is increased
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking. By forming the second circuit over the first circuit with an insulating layer therebetween, the design utilizes the vertical dimension to accommodate both logic and memory functions without expanding the substrate area.
Solution Approach 2:
The circuits are arranged in a nested stacked configuration where the second circuit overlaps with the first circuit in the planar view. This overlapping arrangement maximizes space utilization and minimizes the total area occupied by the integrated circuit.
3Extent of automation
If data is read from memory and written back after logic operation in central processing unit, then logic operation is performed, but the period required for logic operation is increased
Solution Approach 1:
The patent merges the memory circuit and logic circuit into a single integrated device with direct electrical connection. This allows logic operations to be performed directly on data stored in the memory circuit without requiring data to be transferred to and from a separate central processing unit, eliminating I/O wait time and reducing total processing time.
Solution Approach 2:
The integrated circuit is segmented into distinct first and second circuits stacked in different layers. The memory circuit (first circuit) and logic circuit (second circuit) are electrically connected through vertical interconnects, enabling direct data access and processing while maintaining functional separation for optimized performance.
Data Source
AI summary
This invention provides a semiconductor device with high speed operation and reduced size. A circuit includes a circuit including a memory circuit and a circuit including a logic circuit; thus, the circuit functions as a memory device having a function of storing data and a function of performing logic operation. The circuit can output, in addition to data stored in the circuit, data corresponding to a result of logic operation performed using data stored in the circuit as an input signal. The circuit can directly obtain a result of logic operation from the circuit, and thus, the frequency of input/output of a signal performed between the circuit and the circuit can be reduced.