FinFET Capping Layer Planarization via Selective Epitaxial Lateral Overgrowth

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Solution Overview

Problem

The increasing complexity of semiconductor manufacturing due to the scaling down of semiconductor devices, such as finFETs, leads to challenges in reducing contact resistance between epitaxial source/drain regions, which affects the performance and efficiency of integrated circuits.

Innovation Solution

The use of a selective epitaxial lateral overgrowth (ELO) process to grow a capping layer on merged epitaxial regions, controlling the etching gas to deposition gas ratio to achieve a planar and less conformal capping layer surface, which reduces contact resistance and increases the merged area of the source/drain regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional epitaxial growth processes are used, then the manufacturing process is simpler, but the contact resistance between source/drain regions is high and the surface is non-planar

Engineering Contradiction:
Improvecontact resistanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The epitaxial growth process is divided into two distinct stages: initial growth to form the base structure, and selective lateral overgrowth to planarize the surface and reduce contact resistance. This segmentation allows each stage to be optimized independently for its specific function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The initial epitaxial growth stage prepares the substrate and forms the basic source/drain structure before the selective ELO process begins. This preliminary action creates the necessary foundation for the subsequent planarization and contact resistance reduction.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If selective ELO process is used, then contact resistance is reduced and merged area is increased, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvecontact resistanceVSAvoidmanufacturing process ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The selective ELO process applies different growth conditions to different regions of the substrate. By controlling gas flow and temperature locally, the process achieves planar surfaces in contact regions while maintaining the necessary structure in other areas, thereby reducing contact resistance without requiring complete process redesign.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The process utilizes changes in temperature, gas composition, and flow rates during the selective ELO stage to achieve planar surfaces and reduced contact resistance. By carefully adjusting these parameters, the process balances manufacturing complexity with performance improvement.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If non-planar surface is accepted, then manufacturing is easier, but contact resistance increases and device performance decreases

Engineering Contradiction:
Improvesurface planarityVSAvoidcontact resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The selective ELO process introduces lateral dimension control to the epitaxial growth. By promoting lateral overgrowth in specific directions while controlling vertical growth, the process transforms the non-planar surface into a planar one, thereby reducing contact resistance without significantly increasing manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a substantial reduction of contact resistance and an increase in the merged area of the source/drain regions, improving the performance and efficiency of finFETs by achieving a planar top surface with a vertical dimension of less than 5 nm between the highest and lowest points, compared to non-ELO processes which have dimensions greater than 15 nm.

Implementation Method 1

The use of a selective epitaxial lateral overgrowth (ELO) process to grow a capping layer on merged epitaxial regions

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

controlling the etching gas to deposition gas ratio to achieve a planar and less conformal capping layer surface

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS10170370B2Contact resistance control in epitaxial structures of finFET
Publication Date: 2019.01.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10170370B2 patent drawing
  • US10170370B2 patent drawing
  • US10170370B2 patent drawing

AI summary

A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.